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公开(公告)号:US20240120378A1
公开(公告)日:2024-04-11
申请号:US18453529
申请日:2023-08-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sunme Lim , Joongwon Jeon
IPC: H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775
CPC classification number: H01L29/0692 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775
Abstract: A semiconductor device may include a substrate including a first and a second row region, wherein a surface of the substrate is disposed in a first direction and a second direction perpendicular to the first direction, a first nanosheet structure on the first row region and including active segments disposed in the first direction, and the active segments having different widths in the second direction; and a second nanosheet structure on the second row region, the second nanosheet structure spaced apart from the first nanosheet structure in the second direction, and wherein the second nanosheet structure is symmetrical to the first nanosheet structure in the first direction. In a plan view, in each of the first and second nanosheet structures, transition regions between adjacent ones of the active segments have one of a same first angle and a second angle with respect to the first direction.
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公开(公告)号:US11923317B2
公开(公告)日:2024-03-05
申请号:US17230416
申请日:2021-04-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Changjoon Yoon , Sunme Lim , Kyeong-Yeol Kwak , Soojung Kim
IPC: H01L21/66 , G03F7/00 , H01L23/528 , H01L23/544
CPC classification number: H01L23/544 , G03F7/70483 , H01L22/32 , H01L23/528
Abstract: Disclosed is a semiconductor device comprising a substrate, a first lower pattern group on the substrate and including a first key pattern and first lower test patterns horizontally spaced apart from the first key pattern, and a first upper pattern group on the first lower pattern group and including first pads horizontally spaced apart from each other and first upper test patterns between adjacent ones of the first pads. The first key pattern is configured to be used for a photography process associated with fabrication of the semiconductor device. The first pads are electrically connected to the first upper test patterns. One of the first pads vertically overlaps with the first key pattern.
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