公开(公告)号：US11557653B2

公开(公告)日：2023-01-17

申请号：US17345241

申请日：2021-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojin Jeong ,  Sunwook Kim ,  Junbeom Park ,  Seungmin Song

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/16 ,  H01L27/088

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate, a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction, channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure, a source/drain layer on a portion of the active pattern adjacent the gate structure, the source/drain layer contacting the channels, and a sacrificial pattern on an upper surface of each of opposite edges of the portion of the active pattern in the second direction, the sacrificial pattern contacting a lower portion of a sidewall of the source/drain layer and including silicon-germanium.

公开(公告)号：US11927981B2

公开(公告)日：2024-03-12

申请号：US17749681

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghwan Oh ,  Sunwook Kim ,  Wooil Kim ,  Manhwee Jo

IPC: G06F1/32 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3296

CPC classification number: G06F1/08 ,  G06F1/324 ,  G06F1/3296

Abstract: Disclosed is an integrated circuit, which counts parameters required for a dynamic voltage frequency scaling (DVFS) operation. The integrated circuit includes: an event block accessing a bus, which connects processing devices to each other, and outputting an event signal, based on data transmitted through the bus; a clock counter counting the number of clock signals received from a clock management unit; a plurality of performance counters respectively counting parameters used to calculate a workload, based on the event signal; an interface receiving an operation signal from the DVFS governor, which determines an operation frequency and an operation voltage of a processing device based on the workload, and transmitting the number of clock signals and the parameters to the DVFS governor; and a controller controlling operations of the event block, the clock counter, and the plurality of performance counters, based on the operation signal.

公开(公告)号：US11038018B2

公开(公告)日：2021-06-15

申请号：US16775513

申请日：2020-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojin Jeong ,  Sunwook Kim ,  Junbeom Park ,  Seungmin Song

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/16 ,  H01L29/78

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate, a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction, channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure, a source/drain layer on a portion of the active pattern adjacent the gate structure, the source/drain layer contacting the channels, and a sacrificial pattern on an upper surface of each of opposite edges of the portion of the active pattern in the second direction, the sacrificial pattern contacting a lower portion of a sidewall of the source/drain layer and including silicon-germanium.

公开(公告)号：US12289911B2

公开(公告)日：2025-04-29

申请号：US18378710

申请日：2023-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojin Jeong ,  Sunwook Kim ,  Junbeom Park ,  Seungmin Song

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/16 ,  H01L29/78 ,  H10D30/62 ,  H10D62/13 ,  H10D62/832 ,  H10D84/83

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate, a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction, channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure, a source/drain layer on a portion of the active pattern adjacent the gate structure, the source/drain layer contacting the channels, and a sacrificial pattern on an upper surface of each of opposite edges of the portion of the active pattern in the second direction, the sacrificial pattern contacting a lower portion of a sidewall of the source/drain layer and including silicon-germanium.

公开(公告)号：US11791381B2

公开(公告)日：2023-10-17

申请号：US18096663

申请日：2023-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojin Jeong ,  Sunwook Kim ,  Junbeom Park ,  Seungmin Song

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L27/0886 ,  H01L29/1608 ,  H01L29/7854

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate, a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction, channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure, a source/drain layer on a portion of the active pattern adjacent the gate structure, the source/drain layer contacting the channels, and a sacrificial pattern on an upper surface of each of opposite edges of the portion of the active pattern in the second direction, the sacrificial pattern contacting a lower portion of a sidewall of the source/drain layer and including silicon-germanium.

公开(公告)号：US20220374038A1

公开(公告)日：2022-11-24

申请号：US17749681

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghwan Oh ,  Sunwook Kim ,  Wooil Kim ,  Manhwee Jo

IPC: G06F1/08

Abstract: Disclosed is an integrated circuit, which counts parameters required for a dynamic voltage frequency scaling (DVFS) operation. The integrated circuit includes: an event block accessing a bus, which connects processing devices to each other, and outputting an event signal, based on data transmitted through the bus; a clock counter counting the number of clock signals received from a clock management unit; a plurality of performance counters respectively counting parameters used to calculate a workload, based on the event signal; an interface receiving an operation signal from the DVFS governor, which determines an operation frequency and an operation voltage of a processing device based on the workload, and transmitting the number of clock signals and the parameters to the DVFS governor; and a controller controlling operations of the event block, the clock counter, and the plurality of performance counters, based on the operation signal.