公开(公告)号：US09053971B2

公开(公告)日：2015-06-09

申请号：US14052097

申请日：2013-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun Park ,  Han-Young Kim ,  Joon Kim ,  Hyun Park ,  Junghwan Oh ,  Minhee Cho

IPC: H01L21/02 ,  H01L29/94 ,  H01L27/108 ,  H01L21/20 ,  H01L49/02

CPC classification number: H01L28/91 ,  H01L21/28562 ,  H01L21/31116 ,  H01L27/10852

Abstract: A semiconductor device includes a plurality of capacitors disposed on a substrate and a support pattern supporting upper portions and lower portions of the capacitors. Each of the capacitors includes a lower electrode, an upper electrode, and a dielectric layer between the lower and upper electrodes. The lower electrode includes a first electrode portion electrically connected to the substrate and having a solid shape and a second electrode portion stacked on the first electrode portion and having a shape comprising an opening therein. The support pattern includes an upper pattern contacting sidewalls of top end portions of the lower electrodes and a lower pattern vertically spaced apart from the upper pattern. The lower pattern contacts sidewalls under the top end portions of the lower electrodes.

Abstract translation: 半导体器件包括设置在基板上的多个电容器和支撑电容器的上部和下部的支撑图案。 每个电容器包括在下电极和上电极之间的下电极，上电极和电介质层。 下电极包括电连接到基板并具有固体形状的第一电极部分和堆叠在第一电极部分上并具有包括其中的开口的形状的第二电极部分。 支撑图案包括接触下部电极的顶端部的侧壁的上部图案和与上部图案垂直间隔开的下部图案。 下部图案接触下部电极的顶端部分的侧壁。

公开(公告)号：US11610891B2

公开(公告)日：2023-03-21

申请号：US17725806

申请日：2022-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehwan Cho ,  Junghwan Oh ,  Sangho Lee ,  Junwon Lee ,  Jinwoo Bae ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108

Abstract: A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode.

公开(公告)号：US20140110824A1

公开(公告)日：2014-04-24

申请号：US14052097

申请日：2013-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun Park ,  Han-Young Kim ,  Joon Kim ,  Hyun Park ,  Junghwan Oh ,  Minhee Cho

IPC: H01L49/02

CPC classification number: H01L28/91 ,  H01L21/28562 ,  H01L21/31116 ,  H01L27/10852

Abstract: A semiconductor device includes a plurality of capacitors disposed on a substrate and a support pattern supporting upper portions and lower portions of the capacitors. Each of the capacitors includes a lower electrode, an upper electrode, and a dielectric layer between the lower and upper electrodes. The lower electrode includes a first electrode portion electrically connected to the substrate and having a solid shape and a second electrode portion stacked on the first electrode portion and having a shape comprising an opening therein. The support pattern includes an upper pattern contacting sidewalls of top end portions of the lower electrodes and a lower pattern vertically spaced apart from the upper pattern. The lower pattern contacts sidewalls under the top end portions of the lower electrodes.

Abstract translation: 半导体器件包括设置在基板上的多个电容器和支撑电容器的上部和下部的支撑图案。 每个电容器包括在下电极和上电极之间的下电极，上电极和电介质层。 下电极包括电连接到基板并具有固体形状的第一电极部分和堆叠在第一电极部分上并具有包括其中的开口的形状的第二电极部分。 支撑图案包括接触下部电极的顶端部的侧壁的上部图案和与上部图案垂直间隔开的下部图案。 下部图案接触下部电极的顶端部分的侧壁。

公开(公告)号：US11927981B2

公开(公告)日：2024-03-12

申请号：US17749681

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghwan Oh ,  Sunwook Kim ,  Wooil Kim ,  Manhwee Jo

IPC: G06F1/32 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3296

CPC classification number: G06F1/08 ,  G06F1/324 ,  G06F1/3296

Abstract: Disclosed is an integrated circuit, which counts parameters required for a dynamic voltage frequency scaling (DVFS) operation. The integrated circuit includes: an event block accessing a bus, which connects processing devices to each other, and outputting an event signal, based on data transmitted through the bus; a clock counter counting the number of clock signals received from a clock management unit; a plurality of performance counters respectively counting parameters used to calculate a workload, based on the event signal; an interface receiving an operation signal from the DVFS governor, which determines an operation frequency and an operation voltage of a processing device based on the workload, and transmitting the number of clock signals and the parameters to the DVFS governor; and a controller controlling operations of the event block, the clock counter, and the plurality of performance counters, based on the operation signal.

公开(公告)号：US20220374038A1

公开(公告)日：2022-11-24

申请号：US17749681

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghwan Oh ,  Sunwook Kim ,  Wooil Kim ,  Manhwee Jo

IPC: G06F1/08

Abstract: Disclosed is an integrated circuit, which counts parameters required for a dynamic voltage frequency scaling (DVFS) operation. The integrated circuit includes: an event block accessing a bus, which connects processing devices to each other, and outputting an event signal, based on data transmitted through the bus; a clock counter counting the number of clock signals received from a clock management unit; a plurality of performance counters respectively counting parameters used to calculate a workload, based on the event signal; an interface receiving an operation signal from the DVFS governor, which determines an operation frequency and an operation voltage of a processing device based on the workload, and transmitting the number of clock signals and the parameters to the DVFS governor; and a controller controlling operations of the event block, the clock counter, and the plurality of performance counters, based on the operation signal.

公开(公告)号：US11322499B2

公开(公告)日：2022-05-03

申请号：US16943019

申请日：2020-07-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehwan Cho ,  Junghwan Oh ,  Sangho Lee ,  Junwon Lee ,  Jinwoo Bae ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108

Abstract: A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode.

公开(公告)号：US09331140B2

公开(公告)日：2016-05-03

申请号：US14703933

申请日：2015-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun Park ,  Han-Young Kim ,  Joon Kim ,  Hyun Park ,  Junghwan Oh ,  Minhee Cho

IPC: H01L21/02 ,  H01L27/108 ,  H01L21/20 ,  H01L49/02 ,  H01L21/285 ,  H01L21/311

CPC classification number: H01L28/91 ,  H01L21/28562 ,  H01L21/31116 ,  H01L27/10852

Abstract: A semiconductor device includes a plurality of capacitors disposed on a substrate and a support pattern supporting upper portions and lower portions of the capacitors. Each of the capacitors includes a lower electrode, an upper electrode, and a dielectric layer between the lower and upper electrodes. The lower electrode includes a first electrode portion electrically connected to the substrate and having a solid shape and a second electrode portion stacked on the first electrode portion and having a shape comprising an opening therein. The support pattern includes an upper pattern contacting sidewalls of top end portions of the lower electrodes and a lower pattern vertically spaced apart from the upper pattern. The lower pattern contacts sidewalls under the top end portions of the lower electrodes.

公开(公告)号：US20150236084A1

公开(公告)日：2015-08-20

申请号：US14703933

申请日：2015-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun Park ,  Han-Young Kim ,  Joon Kim ,  Hyun Park ,  Junghwan Oh ,  Minhee Cho

IPC: H01L49/02 ,  H01L21/311 ,  H01L21/285

CPC classification number: H01L28/91 ,  H01L21/28562 ,  H01L21/31116 ,  H01L27/10852

Abstract: A semiconductor device includes a plurality of capacitors disposed on a substrate and a support pattern supporting upper portions and lower portions of the capacitors. Each of the capacitors includes a lower electrode, an upper electrode, and a dielectric layer between the lower and upper electrodes. The lower electrode includes a first electrode portion electrically connected to the substrate and having a solid shape and a second electrode portion stacked on the first electrode portion and having a shape comprising an opening therein. The support pattern includes an upper pattern contacting sidewalls of top end portions of the lower electrodes and a lower pattern vertically spaced apart from the upper pattern. The lower pattern contacts sidewalls under the top end portions of the lower electrodes.

Abstract translation: 半导体器件包括设置在基板上的多个电容器和支撑电容器的上部和下部的支撑图案。 每个电容器包括在下电极和上电极之间的下电极，上电极和电介质层。 下电极包括电连接到基板并具有固体形状的第一电极部分和堆叠在第一电极部分上并具有包括其中的开口的形状的第二电极部分。 支撑图案包括接触下部电极的顶端部的侧壁的上部图案和与上部图案垂直间隔开的下部图案。 下部图案接触下部电极的顶端部分的侧壁。