公开(公告)号：US20190157291A1

公开(公告)日：2019-05-23

申请号：US15988745

申请日：2018-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hee-Sung KAM ,  TaeHee LEE ,  Kyoung-Hoon KIM

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  G11C16/08

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/08 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: Provided is a three-dimensional semiconductor memory device. The device may include a substrate that includes a cell array region and a connection region; an electrode structure provided on the substrate to extend in a first direction and include electrodes that are vertically stacked on the substrate and include pad portions which are stacked on the connection region to have a staircase structure; cell vertical structures provided on the cell array region to penetrate the electrode structure; dummy vertical structures provided on the connection region to penetrate the pad portion of each electrode; and cell contact plugs coupled to the pad portions of the electrodes. Each cell contact plug may have a non-circular top surface, and the dummy vertical structures may be arranged to surround each cell contact plug, in a plan view.