公开(公告)号：US20250140727A1

公开(公告)日：2025-05-01

申请号：US18891191

申请日：2024-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonbin Shin ,  Jihye Shim ,  Seokkyu Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/49

Abstract: Provided is a wiring structure including a wiring insulating layer including a first insulating layer and a second insulating layer on the first insulating layer, and a wiring pattern that penetrates the second insulating layer and extends into the first insulating layer, wherein a portion of a side surface of the wiring pattern in contact with the first insulating layer is a curved surface with a first surface roughness, and a portion of the side surface of the wiring pattern in contact with the second insulating layer is a flat surface with a second surface roughness that is less than the first surface roughness.

公开(公告)号：US20250132202A1

公开(公告)日：2025-04-24

申请号：US18816416

申请日：2024-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokkyu Lee ,  Wonbin Shin ,  Kiseok Kim ,  Jihye Shim ,  Jeonggi Jin

IPC: H01L21/768

Abstract: A method of manufacturing a semiconductor package with a semiconductor chip including an active surface and an inactive surface opposite to the active surface is presented. The method includes attaching, to the active surface, a film structure including an insulating layer and a first seed layer contacting the insulating layer. A via hole is formed by penetrating the insulating layer and the first seed layer followed by a descumming the insulating layer and the first seed layer in which the via hole is formed. A second seed layer is formed on the insulating layer and on the first seed layer on which the descum process was performed. A photoresist pattern on the second seed layer enables forming a conductive via by filling both a space defined by the via hole with a conductive material and by filling a space defined by the photoresist pattern with the conductive material.

公开(公告)号：US20240194582A1

公开(公告)日：2024-06-13

申请号：US18523970

申请日：2023-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokkyu Lee ,  Jihye Shim ,  Kiseok Kim ,  Wonbin Shin

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49894 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/08 ,  H01L2224/08235

Abstract: A semiconductor package includes a redistribution substrate having a first surface and a second surface opposite to each other, and including a plurality of first photosensitive insulating layers and a plurality of redistribution layers disposed among the plurality of first photosensitive insulating layers; at least one semiconductor chip disposed on the first surface of the redistribution substrate and including a plurality of contact pads electrically connected to the plurality of redistribution layers; a protective insulating layer including a second photosensitive insulating layer disposed on the second surface of the redistribution substrate and having a plurality of contact holes, and a non-photosensitive insulating layer disposed on an outer surface of the second photosensitive insulating layer and an internal sidewall of each of the plurality of contact holes; and a plurality of under bump metallurgy (UBM) connectors each having a UBM pad disposed on the protective insulating layer and a UBM via disposed in a respective contact hole of the plurality of contact holes and electrically connected to the plurality of redistribution layers.