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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210126090A1

    公开(公告)日：2021-04-29

    申请号：US16897492

    申请日：2020-06-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hui-Jung KIM ,  Kyu Jin KIM ,  Sang-Il HAN ,  Kyu Hyun LEE ,  Woo Young CHOI ,  Yoo Sang HWANG

    IPC: H01L29/06 ,  H01L29/423

    Abstract: A semiconductor device including a device isolation layer defining an active region; a first trench in the device isolation layer; a second trench in the active region; a main gate electrode structure filling a portion of the first trench and including a first barrier conductive layer and a main gate electrode; a pass gate electrode structure filling a portion of the second trench and including a second barrier conductive layer and a pass gate electrode; a support structure filling another portion of the second trench above the pass gate electrode; a first capping pattern filling another portion of the first trench above the main gate electrode; and a second gate insulating layer extending along a bottom and sidewall of the second trench, wherein the second barrier conductive layer is between the second gate insulating layer and the pass gate electrode and extends along a bottom and sidewall thereof.

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220149153A1

    公开(公告)日：2022-05-12

    申请号：US17587444

    申请日：2022-01-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hui-Jung KIM ,  Kyu Jin KIM ,  Sang-Il HAN ,  Kyu Hyun LEE ,  Woo Young CHOI ,  Yoo Sang HWANG

    IPC: H01L29/06 ,  H01L29/423

    Abstract: A semiconductor device including a device isolation layer defining an active region; a first trench in the device isolation layer; a second trench in the active region; a main gate electrode structure filling a portion of the first trench and including a first barrier conductive layer and a main gate electrode; a pass gate electrode structure filling a portion of the second trench and including a second barrier conductive layer and a pass gate electrode; a support structure filling another portion of the second trench above the pass gate electrode; a first capping pattern filling another portion of the first trench above the main gate electrode; and a second gate insulating layer extending along a bottom and sidewall of the second trench, wherein the second barrier conductive layer is between the second gate insulating layer and the pass gate electrode and extends along a bottom and sidewall thereof.

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240064968A1

    公开(公告)日：2024-02-22

    申请号：US18321511

    申请日：2023-05-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Woo Young CHOI ,  Hui-Jung KIM ,  Ji Hoon SUNG ,  Ga Eun CHOI ,  Sang Kyu SUN

    IPC: H10B12/00

    CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/34 ,  H10B12/485 ,  H10B12/02

    Abstract: Provided is a semiconductor memory device comprising an active region extending in a cell isolation layer, wherein the active region includes a first region and a second region; a bit line intersects the active region; a bit line contact between a substrate and the bit line, wherein the bit line contact is electrically connected to the first region; a bit line spacer that is on side surfaces of the bit line and the bit line contact; a node pad on a lateral side of the bit line spacer, wherein the node pad is electrically connected to the second region; a storage contact that is on the node pad and on a side surface of the bit line spacer, wherein the storage contact includes a first part having a first width and a second part having a second width different from the first width.

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