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公开(公告)号:US20240357795A1
公开(公告)日:2024-10-24
申请号:US18513011
申请日:2023-11-17
发明人: Tae Jin PARK , Hui-Jung KIM , Sang Jae PARK , Ki Seok LEE , Myeong-Dong LEE
IPC分类号: H10B12/00
CPC分类号: H10B12/315 , H10B12/0335
摘要: There is provided a semiconductor memory device comprising: a substrate; a base insulating film on an upper surface of the substrate; a plurality of first conductive patterns on the base insulating film and spaced apart from each other, wherein the plurality of first conductive patterns extend in a first direction; a spacer structure on a side surface of each of the plurality of first conductive patterns; a barrier metal film on a side surface of the spacer structure, wherein the barrier metal film extends through the base insulating film to be electrically connected to the substrate; a filling metal film on the barrier metal film, wherein the filling metal film fills at least a portion of a space between adjacent ones of the plurality of first conductive patterns; and a capacitor structure on the filling metal film, wherein the capacitor structure is electrically connected to the filling metal film.
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公开(公告)号:US20230189501A1
公开(公告)日:2023-06-15
申请号:US18165692
申请日:2023-02-07
发明人: Hui-Jung KIM , Taehyun An , Kiseok Lee , Yoosang Hwang
摘要: A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.
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公开(公告)号:US20210043629A1
公开(公告)日:2021-02-11
申请号:US16880230
申请日:2020-05-21
发明人: Hui-Jung KIM , Taehyun AN , Kiseok LEE , Keunnam KIM , Yoosang HWANG
IPC分类号: H01L27/108 , G11C5/06
摘要: A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.
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公开(公告)号:US20200243532A1
公开(公告)日:2020-07-30
申请号:US16851957
申请日:2020-04-17
发明人: Hui-Jung KIM , Sung-hee HAN , Ki-seok LEE , Bong-Soo KIM , Yoo-sang HWANG
IPC分类号: H01L27/108 , H01L49/02
摘要: An integrated circuit device may include a support pattern over a substrate, a lower electrode pattern and a dielectric structure over the substrate, and an upper electrode structure on the dielectric structure. The support pattern may include a first support structure extending in a vertical direction. The lower electrode pattern may be between the support pattern and the dielectric structure. The lower electrode pattern may include a first group of N (e.g., an integer of 4 or more) lower electrodes that are spaced apart from each other and may extend in the vertical direction to a first level above the substrate. The dielectric structure may include a first dielectric protrusion that extends in the vertical direction and surrounds the first support structure and the first group of N lower electrodes. The upper electrode structure may include a first upper electrode protrusion that surrounds the first dielectric protrusion.
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公开(公告)号:US20210257374A1
公开(公告)日:2021-08-19
申请号:US17035082
申请日:2020-09-28
发明人: KI SEOK LEE , Jae Hyun YOON , Kyu Jin KIM , Keun Nam KIM , Hui-Jung KIM , Kyu Hyun LEE , SANG-IL HAN , Sung Hee HAN , Yoo Sang HWANG
IPC分类号: H01L27/108
摘要: A includes an element isolation region, a first active region bounded by the element isolation region and that extends in a first direction and includes first and second parts disposed at a first level, and a third part disposed at a second level located above the first level, and a gate electrode disposed inside each of the element isolation region and the first active region and that extends in a second direction different from the first direction. The second part is spaced apart in the first direction from the first part, and the third part contacts each of the first and second parts. A first width in the second direction of the first part is less than a second width in the second direction of the third part.
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公开(公告)号:US20210126090A1
公开(公告)日:2021-04-29
申请号:US16897492
申请日:2020-06-10
发明人: Hui-Jung KIM , Kyu Jin KIM , Sang-Il HAN , Kyu Hyun LEE , Woo Young CHOI , Yoo Sang HWANG
IPC分类号: H01L29/06 , H01L29/423
摘要: A semiconductor device including a device isolation layer defining an active region; a first trench in the device isolation layer; a second trench in the active region; a main gate electrode structure filling a portion of the first trench and including a first barrier conductive layer and a main gate electrode; a pass gate electrode structure filling a portion of the second trench and including a second barrier conductive layer and a pass gate electrode; a support structure filling another portion of the second trench above the pass gate electrode; a first capping pattern filling another portion of the first trench above the main gate electrode; and a second gate insulating layer extending along a bottom and sidewall of the second trench, wherein the second barrier conductive layer is between the second gate insulating layer and the pass gate electrode and extends along a bottom and sidewall thereof.
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公开(公告)号:US20210005506A1
公开(公告)日:2021-01-07
申请号:US16722622
申请日:2019-12-20
发明人: Kyujin KIM , Hui-Jung KIM , Junsoo KIM , Sangho LEE , Jae-Hwan CHO , Yoosang HWANG
IPC分类号: H01L21/762 , H01L21/311 , H01L21/8234 , H01L29/66 , H01L29/78 , H01L29/423 , H01L27/108
摘要: A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.
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公开(公告)号:US20200227418A1
公开(公告)日:2020-07-16
申请号:US16732925
申请日:2020-01-02
发明人: Hui-Jung KIM , Min Hee CHO , Junsoo KIM , Taehyun An , Dongsoo Woo , Yoosang HWANG
IPC分类号: H01L27/108 , H01L29/06 , H01L29/423 , H01L29/786 , H01L29/66 , H01L21/02
摘要: A semiconductor memory device includes a stack structure having a plurality of layers vertically stacked on a substrate, each layer including, a first bit line and a gate line extending in a first direction, a first semiconductor pattern extending in a second direction between the first bit line and the gate line, the second direction intersecting the first direction, and a second semiconductor pattern adjacent to the gate line across a first gate insulating layer, the second semiconductor pattern extending in the first direction, a first word line adjacent to the first semiconductor pattern and vertically extending in a third direction from the substrate, a second bit line connected to an end of the second semiconductor pattern and vertically extending in the third direction from the substrate, and a second word line connected to another end of the second semiconductor pattern and vertically extending in the third direction.
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公开(公告)号:US20160080096A1
公开(公告)日:2016-03-17
申请号:US14848899
申请日:2015-09-09
发明人: Hui-Jung KIM , Hyeong-Seok JEONG , Soo-Yong KIM , Jeong-Yeol BAE , Dong-Han LEE
IPC分类号: H04B17/318 , H04W52/02 , H04W4/00
CPC分类号: H04B17/318 , H04W4/80 , H04W52/0209 , Y02B70/30 , Y02D70/1262 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/162 , Y02D70/22
摘要: A transceiver and a method operating the transceiver are provided. The transceiver includes a first communication module configured to receive a first signal based on a first communication scheme; a second communication module configured to receive a second signal based on a second communication scheme; a reception module having a low-power circuit configured to detect a signal in a frequency band which can be used by the first communication module and the second communication module; and a controller configured to establish channels for the first communication module or the second communication module based on a strength of the signal detected by the reception module.
摘要翻译: 提供了收发器和操作收发器的方法。 收发器包括:第一通信模块,被配置为基于第一通信方案接收第一信号; 第二通信模块,被配置为基于第二通信方案来接收第二信号; 具有低功率电路的接收模块,被配置为检测可由第一通信模块和第二通信模块使用的频带中的信号; 以及控制器,被配置为基于由所述接收模块检测到的信号的强度来建立用于所述第一通信模块或所述第二通信模块的信道。
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公开(公告)号:US20240266408A1
公开(公告)日:2024-08-08
申请号:US18507224
申请日:2023-11-13
发明人: Kiseok LEE , Keunnam KIM , Hui-Jung KIM
IPC分类号: H01L29/417 , H01L27/088
CPC分类号: H01L29/41741 , H01L27/088
摘要: A semiconductor device includes a device isolation part on a substrate and defining active regions that are two-dimensionally disposed in first and second directions, the active regions each extending in the first direction; first and second word lines crossing the active regions in the second direction and adjacent to each other in the first direction; a first impurity region in the active region between the first and second word lines; a second impurity region in the active region at one side of the first word line and spaced apart from the first impurity region; a first conductive pad in contact with the first impurity region; a second conductive pad in contact with the second impurity region; a bit line on the first conductive pad and extending in the first direction; a storage node contact structure on the second conductive pad; and a landing pad on the storage node contact structure.
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