Semiconductor package
    1.
    发明授权

    公开(公告)号:US10741510B2

    公开(公告)日:2020-08-11

    申请号:US16105227

    申请日:2018-08-20

    Abstract: A semiconductor package includes a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, an encapsulant encapsulating at least a portion of the semiconductor chip, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer and a via electrically connected to the connection pads of the semiconductor chip, wherein at least a portion of the redistribution layer and the via is formed of a metal layer having a concave portion depressed from a lower surface thereof and filled with an insulating material.

    Fan-out semiconductor package
    2.
    发明授权

    公开(公告)号:US10790255B2

    公开(公告)日:2020-09-29

    申请号:US16291621

    申请日:2019-03-04

    Abstract: A fan-out semiconductor package includes a frame comprising a plurality of wiring layers electrically connected to one another, and having a recessed portion having a stopper layer 112aM disposed on a bottom surface of the recessed portion, and a through-hole penetrating through the stopper layer; a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and disposed in the recessed portion such that the inactive surface opposes the stopper layer; an encapsulant covering at least portions of the frame and the inactive surface of the semiconductor chip, and filling at least a portion of the recessed portion; and an interconnect structure disposed on the frame and the active surface of the semiconductor chip, and comprising a redistribution layer electrically connected to the plurality of wiring layers and the connection pad.

    FAN-OUT SEMICONDUCTOR PACKAGE
    3.
    发明申请

    公开(公告)号:US20200105703A1

    公开(公告)日:2020-04-02

    申请号:US16291621

    申请日:2019-03-04

    Abstract: A fan-out semiconductor package includes a frame comprising a plurality of wiring layers electrically connected to one another, and having a recessed portion having a stopper layer 112aM disposed on a bottom surface of the recessed portion, and a through-hole penetrating through the stopper layer; a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and disposed in the recessed portion such that the inactive surface opposes the stopper layer; an encapsulant covering at least portions of the frame and the inactive surface of the semiconductor chip, and filling at least a portion of the recessed portion; and an interconnect structure disposed on the frame and the active surface of the semiconductor chip, and comprising a redistribution layer electrically connected to the plurality of wiring layers and the connection pad.

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