公开(公告)号：US20250054870A1

公开(公告)日：2025-02-13

申请号：US18926130

申请日：2024-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woonchun Kim ,  Seungwan Shin ,  Gun Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/10

Abstract: A semiconductor package includes; a first redistribution structure including first redistribution conductors, a semiconductor chip on the first redistribution structure and including connection pads electrically connecting the first redistribution conductors, a connection conductor on the first redistribution structure, laterally spaced apart from the semiconductor chip, and electrically connected to the first redistribution conductors, an encapsulant on the first redistribution structure and sealing the semiconductor chip and at least a portion of the connection conductor, a barrier layer extending along an upper surface of the encapsulant, and a second redistribution conductor on the barrier layer and penetrating the barrier layer to contact the connection conductor.

公开(公告)号：US12154859B2

公开(公告)日：2024-11-26

申请号：US17707002

申请日：2022-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woonchun Kim ,  Seungwan Shin ,  Gun Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/10

Abstract: A semiconductor package includes; a first redistribution structure including first redistribution conductors, a semiconductor chip on the first redistribution structure and including connection pads electrically connecting the first redistribution conductors, a connection conductor on the first redistribution structure, laterally spaced apart from the semiconductor chip, and electrically connected to the first redistribution conductors, an encapsulant on the first redistribution structure and sealing the semiconductor chip and at least a portion of the connection conductor, a barrier layer extending along an upper surface of the encapsulant, and a second redistribution conductor on the barrier layer and penetrating the barrier layer to contact the connection conductor.

公开(公告)号：US11837537B2

公开(公告)日：2023-12-05

申请号：US17403233

申请日：2021-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongju Cho ,  Myungsam Kang ,  Younggwan Ko ,  Gun Lee ,  Jaekul Lee

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L23/3157 ,  H01L23/49531 ,  H01L23/49534 ,  H01L23/5283 ,  H01L24/09 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2924/3511

Abstract: A fan-out semiconductor package includes a first connection structure having first and second surfaces, a first semiconductor chip disposed on the first surface, a first encapsulant disposed on the first surface and covering at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the second surface, one or more first metal members disposed on the second surface, one or more second metal members disposed on the second surface, a second encapsulant disposed on the second surface and respectively covering at least portions of the second semiconductor chip and the first and second metal members, and a second connection structure disposed on an opposite side of a side of the second encapsulant, on which the first connection structure is disposed.

公开(公告)号：US20240080994A1

公开(公告)日：2024-03-07

申请号：US18446544

申请日：2023-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gun Lee ,  Junwoo Myung ,  Yuseon Heo

IPC: H05K3/46 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K3/465 ,  H05K1/0296 ,  H05K1/0306 ,  H05K1/114 ,  H05K3/0023 ,  H05K3/4661 ,  H05K3/4679 ,  H05K2201/09563 ,  H05K2201/096

Abstract: In fabricating a wiring structure, a first wiring is formed on a substrate. First and second light sensitive insulation layers that are reactive to light of first and second wavelength ranges, respectively, are sequentially formed on the first wiring. First and second exposing processes are performed using the light of the first and second wavelength ranges, respectively, to form first and second exposed portions in the first and second light sensitive insulation layers, respectively. The first and second exposed portions are removed by a developing process to form a hole and an opening, respectively. The hole and the opening extend through the first and second light sensitive insulation layers, respectively, to be connected to one another. A conductive layer is formed in the hole and in the opening, and is planarized to form a first via and a second wiring in the hole and in the opening, respectively.

公开(公告)号：US11127692B2

公开(公告)日：2021-09-21

申请号：US16393073

申请日：2019-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gun Lee ,  Jun Gul Hwang ,  Ji Eun Woo ,  Sung Keun Park

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L23/485

Abstract: A semiconductor package includes a semiconductor chip, and a connection structure disposed on at least one side of the semiconductor chip, and including an insulating layer and a redistribution layer electrically connected to the semiconductor chip, wherein the redistribution layer includes a plurality of conductive patterns, and at least two of the plurality of conductive patterns have different degrees of surface roughness, and a conductive pattern having a higher surface roughness has a width wider than a width of a conductive pattern having a lower surface roughness.

公开(公告)号：US10790255B2

公开(公告)日：2020-09-29

申请号：US16291621

申请日：2019-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woon Chun Kim ,  Jun Heyoung Park ,  Ji Hye Shim ,  Sung Keun Park ,  Gun Lee

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/13 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A fan-out semiconductor package includes a frame comprising a plurality of wiring layers electrically connected to one another, and having a recessed portion having a stopper layer 112aM disposed on a bottom surface of the recessed portion, and a through-hole penetrating through the stopper layer; a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and disposed in the recessed portion such that the inactive surface opposes the stopper layer; an encapsulant covering at least portions of the frame and the inactive surface of the semiconductor chip, and filling at least a portion of the recessed portion; and an interconnect structure disposed on the frame and the active surface of the semiconductor chip, and comprising a redistribution layer electrically connected to the plurality of wiring layers and the connection pad.

公开(公告)号：US20200168562A1

公开(公告)日：2020-05-28

申请号：US16393073

申请日：2019-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gun Lee ,  Jun Gul Hwang ,  Ji Eun Woo ,  Sung Keun Park

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552

Abstract: A semiconductor package includes a semiconductor chip, and a connection structure disposed on at least one side of the semiconductor chip, and including an insulating layer and a redistribution layer electrically connected to the semiconductor chip, wherein the redistribution layer includes a plurality of conductive patterns, and at least two of the plurality of conductive patterns have different degrees of surface roughness, and a conductive pattern having a higher surface roughness has a width wider than a width of a conductive pattern having a lower surface roughness.

公开(公告)号：US20200105703A1

公开(公告)日：2020-04-02

申请号：US16291621

申请日：2019-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woon Chun Kim ,  Jun Heyoung Park ,  Ji Hye Shim ,  Sung Keun Park ,  Gun Lee

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/13 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A fan-out semiconductor package includes a frame comprising a plurality of wiring layers electrically connected to one another, and having a recessed portion having a stopper layer 112aM disposed on a bottom surface of the recessed portion, and a through-hole penetrating through the stopper layer; a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and disposed in the recessed portion such that the inactive surface opposes the stopper layer; an encapsulant covering at least portions of the frame and the inactive surface of the semiconductor chip, and filling at least a portion of the recessed portion; and an interconnect structure disposed on the frame and the active surface of the semiconductor chip, and comprising a redistribution layer electrically connected to the plurality of wiring layers and the connection pad.

公开(公告)号：US20240128171A1

公开(公告)日：2024-04-18

申请号：US18204241

申请日：2023-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junwoo Myung ,  Gun Lee

IPC: H01L23/498 ,  H01L21/60 ,  H01L23/00 ,  H01L23/14 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L23/49816 ,  H01L21/60 ,  H01L23/142 ,  H01L23/485 ,  H01L23/53228 ,  H01L24/97 ,  H01L2021/60255 ,  H01L2224/97 ,  H01L2924/15311

Abstract: A method of manufacturing a semiconductor package includes applying a cutter to a boundary between a main portion of a second metal layer and an edge portion of the second metal layer that surrounds the main portion, the second metal layer being on an upper surface of a first metal layer disposed on an upper surface of a carrier substrate, peeling the edge portion of the second metal layer from the first metal layer, forming a cover insulating layer on an upper surface of the main portion of the second metal layer, and disposing a semiconductor chip on an upper surface of the cover insulating layer.

公开(公告)号：US20210375757A1

公开(公告)日：2021-12-02

申请号：US17403233

申请日：2021-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongju Cho ,  Myungsam Kang ,  Yonggwan Ko ,  Gun Lee ,  Jaekul Lee

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/00

Abstract: A fan-out semiconductor package includes a first connection structure having first and second surfaces, a first semiconductor chip disposed on the first surface, a first encapsulant disposed on the first surface and covering at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the second surface, one or more first metal members disposed on the second surface, one or more second metal members disposed on the second surface, a second encapsulant disposed on the second surface and respectively covering at least portions of the second semiconductor chip and the first and second metal members, and a second connection structure disposed on an opposite side of a side of the second encapsulant, on which the first connection structure is disposed.