公开(公告)号：US20240047319A1

公开(公告)日：2024-02-08

申请号：US18125348

申请日：2023-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho PARK ,  Gyuho Kang ,  Sung Keun Park ,  Seong-Hoon Bae ,  Jaemok Jung ,  Ju-ll Choi

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L21/4853 ,  H01L21/563 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/48227 ,  H01L24/48

Abstract: A semiconductor package includes a first substrate, a semiconductor chip on the first substrate, a second substrate spaced apart from the first substrate, a wire spaced apart from a lateral surface of the semiconductor chip and connecting the first substrate to the second substrate, a mold structure on a top surface of the semiconductor chip, the lateral surface of the semiconductor chip, and a lateral surface of the wire, and an under-fill pattern on the lateral surface of the wire and is between the wire and the mold structure.

公开(公告)号：US11127692B2

公开(公告)日：2021-09-21

申请号：US16393073

申请日：2019-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gun Lee ,  Jun Gul Hwang ,  Ji Eun Woo ,  Sung Keun Park

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L23/485

Abstract: A semiconductor package includes a semiconductor chip, and a connection structure disposed on at least one side of the semiconductor chip, and including an insulating layer and a redistribution layer electrically connected to the semiconductor chip, wherein the redistribution layer includes a plurality of conductive patterns, and at least two of the plurality of conductive patterns have different degrees of surface roughness, and a conductive pattern having a higher surface roughness has a width wider than a width of a conductive pattern having a lower surface roughness.

公开(公告)号：US10790255B2

公开(公告)日：2020-09-29

申请号：US16291621

申请日：2019-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woon Chun Kim ,  Jun Heyoung Park ,  Ji Hye Shim ,  Sung Keun Park ,  Gun Lee

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/13 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A fan-out semiconductor package includes a frame comprising a plurality of wiring layers electrically connected to one another, and having a recessed portion having a stopper layer 112aM disposed on a bottom surface of the recessed portion, and a through-hole penetrating through the stopper layer; a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and disposed in the recessed portion such that the inactive surface opposes the stopper layer; an encapsulant covering at least portions of the frame and the inactive surface of the semiconductor chip, and filling at least a portion of the recessed portion; and an interconnect structure disposed on the frame and the active surface of the semiconductor chip, and comprising a redistribution layer electrically connected to the plurality of wiring layers and the connection pad.

公开(公告)号：US20200168562A1

公开(公告)日：2020-05-28

申请号：US16393073

申请日：2019-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gun Lee ,  Jun Gul Hwang ,  Ji Eun Woo ,  Sung Keun Park

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552

Abstract: A semiconductor package includes a semiconductor chip, and a connection structure disposed on at least one side of the semiconductor chip, and including an insulating layer and a redistribution layer electrically connected to the semiconductor chip, wherein the redistribution layer includes a plurality of conductive patterns, and at least two of the plurality of conductive patterns have different degrees of surface roughness, and a conductive pattern having a higher surface roughness has a width wider than a width of a conductive pattern having a lower surface roughness.

公开(公告)号：US20200105703A1

公开(公告)日：2020-04-02

申请号：US16291621

申请日：2019-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woon Chun Kim ,  Jun Heyoung Park ,  Ji Hye Shim ,  Sung Keun Park ,  Gun Lee

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/13 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A fan-out semiconductor package includes a frame comprising a plurality of wiring layers electrically connected to one another, and having a recessed portion having a stopper layer 112aM disposed on a bottom surface of the recessed portion, and a through-hole penetrating through the stopper layer; a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and disposed in the recessed portion such that the inactive surface opposes the stopper layer; an encapsulant covering at least portions of the frame and the inactive surface of the semiconductor chip, and filling at least a portion of the recessed portion; and an interconnect structure disposed on the frame and the active surface of the semiconductor chip, and comprising a redistribution layer electrically connected to the plurality of wiring layers and the connection pad.

公开(公告)号：US10923420B2

公开(公告)日：2021-02-16

申请号：US15873352

申请日：2018-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： In Wook Oh ,  Dong Hyun Kim ,  Doo Hwan Park ,  Sung Keun Park ,  Chul Hong Park ,  Sung Wook Hwang

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L23/532 ,  H01L21/285

Abstract: A semiconductor device includes a plurality of main contact plugs and a plurality of dummy contact plugs which pass through an insulating layer on a substrate. A plurality of upper interconnections is on the insulating layer. The plurality of dummy contact plugs include a first dummy contact plug. The plurality of upper interconnections include a first upper interconnection overlapping the first dummy contact plug. A vertical central axis of the first dummy contact plug is located outside the first upper interconnection.