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公开(公告)号:US20220383790A1
公开(公告)日:2022-12-01
申请号:US17745246
申请日:2022-05-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jeeyeon EOM , Jeonghoon CHOI , Yeongshin JANG , Youngbae MOON , Woonyoung LEE
IPC: G09G3/20
Abstract: Provided is a display driving circuit including a plurality of source channels configured to provide data voltages to a plurality of data lines of a display panel, respectively; a dummy channel on one side of at least one of the source channels; and control logic configured to control operations of the source channels and the dummy channel, wherein, when failure of a first source channel from among the source channels is determined, the control logic is further configured to provide data voltages to data lines corresponding to the first source channel and second source channels, respectively, which are between the first source channel and the dummy channel, by using the second source channels and the dummy channel.
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公开(公告)号:US20230410708A1
公开(公告)日:2023-12-21
申请号:US18241177
申请日:2023-08-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Wonseok KIM , Woonyoung LEE , Yeongshin JANG
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2330/021 , G09G2310/08 , G09G2310/0275
Abstract: A display apparatus including a display driving circuit and a display panel is provided. The display driving circuit, connected to a display panel including a plurality of pixel groups, includes a controller configured to determine a driving order of each of the plurality of pixel groups in a first horizontal period and to generate image data and a selection signal in a first voltage range, a data driver configured to generate an image signal on the basis of the image data and to transfer the image signal to the plurality of data lines in the first horizontal period, a plurality of output pads respectively connected to the plurality of pixel groups through the plurality of data lines, and a data switching circuit configured to provide the image signal to the display panel through at least one of the plurality of output pads based on the selection signal.
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公开(公告)号:US20230326425A1
公开(公告)日:2023-10-12
申请号:US18097948
申请日:2023-01-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kyounghwan KWON , Wonseok KIM , Wangsuk SUNG , Sangmin LEE , Seonmee LEE , Woonyoung LEE
IPC: G09G5/00
CPC classification number: G09G5/003 , G09G2310/0243
Abstract: An operating method of a display driver integrated circuit (DDI) includes determining whether a change to a level of a first logic voltage supplied to a logic circuit of the DDI is required, based on determining that a change to the level of the first logic voltage is required, transmitting a logic voltage setting command to a power management integrated circuit (PMIC), and receiving, from the PMIC, a second logic voltage having a level different from the first logic voltage and corresponding to the logic voltage setting command.
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公开(公告)号:US20220262292A1
公开(公告)日:2022-08-18
申请号:US17589997
申请日:2022-02-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Wonseok KIM , Woonyoung LEE , Yeongshin JANG
IPC: G09G3/20
Abstract: A display apparatus including a display driving circuit and a display panel is provided. The display driving circuit, connected to a display panel including a plurality of pixel groups, includes a controller configured to determine a driving order of each of the plurality of pixel groups in a first horizontal period and to generate image data and a selection signal in a first voltage range, a data driver configured to generate an image signal on the basis of the image data and to transfer the image signal to the plurality of data lines in the first horizontal period, a plurality of output pads respectively connected to the plurality of pixel groups through the plurality of data lines, and a data switching circuit configured to provide the image signal to the display panel through at least one of the plurality of output pads based on the selection signal.
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公开(公告)号:US20220109415A1
公开(公告)日:2022-04-07
申请号:US17232762
申请日:2021-04-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Youngbae MOON , Woonyoung LEE , Chanbong YU , Yunseok JANG
IPC: H03F3/45 , H02H9/04 , G09G3/3275
Abstract: An output buffer circuit includes an operational amplifier configured to generate an amplifier output voltage signal based on an input voltage signal and on a compensation current, a slew rate compensating circuit configured to generate the compensation current to increase a slew rate of the amplifier output voltage signal based on a difference between the input voltage signal and a feedback voltage signal, an output path circuit connected between the operational amplifier and an output pad, the output path circuit configured to transfer the amplifier output voltage signal to generate a pad output voltage signal through the output pad, and a feedback path circuit, the feedback path circuit connected between the slew rate compensating circuit and a feedback input node that is on the output path circuit, the feedback path circuit configured to generate the feedback voltage signal.
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