公开(公告)号：US20230261106A1

公开(公告)日：2023-08-17

申请号：US18092246

申请日：2022-12-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wooyeol Maeng ,  Hyungjin Lee ,  Huichul Shin

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L21/265 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0878 ,  H01L29/4966 ,  H01L29/7851 ,  H01L21/26513 ,  H01L21/28088 ,  H01L29/66545 ,  H01L29/66681

Abstract: A transistor includes a substrate including a P-type-sub region doped with P-type impurities, a well region positioned at an upper portion of the substrate and doped with P-type impurities, a gate structure on the well region, and drain and source regions. The gate structure includes a gate insulation layer, first and second conductive patterns for adjusting a threshold voltage and a gate electrode. The drain and source regions are positioned at an upper portion of the substrate adjacent first and second sidewalk of the gate structure, respectively. The source region is doped with N-type impurities. The drain region includes a highly doped N-type impurity region, an N-type impurity region, and a lightly doped P-type impurity region sequentially disposed in a downward direction from a top surface of the substrate. A boundary between the well region and the P-type sub region is positioned under a bottom of the drain region.