公开(公告)号：US20140116761A1

公开(公告)日：2014-05-01

申请号：US14049701

申请日：2013-10-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Eun Lee ,  Byoung Hwa Lee ,  Yee Na Shin ,  Yul Kyo Chung

IPC: H05K1/18

CPC classification number: H05K1/185 ,  H01G4/232 ,  H01G4/30 ,  H05K1/0271 ,  H05K3/0035 ,  H05K3/0047 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611

Abstract: The present invention relates to a multilayer ceramic capacitor and a printed circuit board including the same that can minimize thickness deviations of an external electrode and a multilayer ceramic. A multilayer ceramic capacitor according to an embodiment of the present invention includes a multilayer ceramic and external electrodes formed on both sides of the multilayer ceramic, wherein |Tmax−Tmin| may be less than 10 μm, and |CTmax−CTmin| may be less than 20 μm. (Here, Tmax is a maximum thickness of the external electrodes in a via processing area, Tmin is a minimum thickness of the external electrodes in the via processing area, CTmax is a maximum thickness of the multilayer ceramic capacitor in the via processing area, and CTmin is a minimum thickness of the multilayer ceramic capacitor in the via processing area.)

Abstract translation: 本发明涉及一种多层陶瓷电容器和包括该多层陶瓷电容器的印刷电路板，其可以使外部电极和多层陶瓷的厚度偏差最小化。 根据本发明实施例的多层陶瓷电容器包括多层陶瓷和形成在多层陶瓷两侧的外部电极，其中| Tmax-Tmin | 可以小于10μm，| CTmax-CTmin | 可以小于20μm。 （Tmax是通孔处理区域中的外部电极的最大厚度，Tmin是通孔处理区域中的外部电极的最小厚度，CTmax是通孔处理区域中的多层陶瓷电容器的最大厚度， CTmin是通孔处理区域中的多层陶瓷电容器的最小厚度。）