公开(公告)号：US10076044B2

公开(公告)日：2018-09-11

申请号：US15027756

申请日：2014-09-24

申请人： HITACHI CHEMICAL COMPANY, LTD.

发明人： Nobuyuki Yoshida

IPC分类号： H05K3/42 ,  H05K3/00 ,  H05K3/46

CPC分类号： H05K3/423 ,  H05K3/0026 ,  H05K3/0035 ,  H05K3/421 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09863 ,  H05K2201/2072 ,  H05K2203/1184 ,  H05K2203/1476 ,  H05K2203/1492

摘要： The present invention is a method for manufacturing a multilayer wiring board having (1) a step of providing with a hole for a via hole from a metal foil for an upper layer wiring pattern to an inner layer wiring pattern by using a conformal method or a direct laser method, and (2) a step of forming a via hole by forming electrolytic filling plating layers in the hole for a via hole, wherein the formation of the electrolytic filling plating layers in the step (2) is carried out by repeating change in electric current density of temporarily decreasing the electric current density of electrolytic filling plating in the middle of the electrolytic filling plating and then increasing it again, two or more times before the electrolytic filling plating layers block an opening of the hole for a via hole.

公开(公告)号：US20180242448A1

公开(公告)日：2018-08-23

申请号：US15896166

申请日：2018-02-14

申请人： ARISAWA MFG. CO., LTD.

发明人： Kazuo YOSHIKAWA ,  Makoto TAI ,  Nobuyuki IWANO ,  Takayuki MAYAMA

IPC分类号： H05K1/03 ,  H05K3/00 ,  C08L53/00 ,  C08K3/36 ,  C09J153/00 ,  B32B7/12 ,  B32B15/08 ,  B32B15/20

CPC分类号： H05K1/036 ,  B32B7/12 ,  B32B15/08 ,  B32B15/20 ,  B32B2250/02 ,  B32B2250/05 ,  B32B2255/10 ,  B32B2255/26 ,  B32B2379/08 ,  B32B2457/08 ,  C08K3/36 ,  C08K2003/2227 ,  C08L53/005 ,  C09J7/10 ,  C09J7/387 ,  C09J153/005 ,  C09J2201/622 ,  C09J2203/326 ,  C09J2205/102 ,  C09J2453/00 ,  H05K1/024 ,  H05K1/0373 ,  H05K1/0393 ,  H05K1/09 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/022 ,  H05K3/386 ,  H05K2201/0112 ,  H05K2201/0133 ,  H05K2201/0154 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/2063 ,  H05K2203/107

摘要： The present invention provides a resin composition comprising a specific styrene polymer, a specific inorganic filler, and a curing agent, wherein the styrene polymer is a specific acid-modified styrene polymer, and the resin composition satisfies specific conditions in the form of a film having a thickness of 25 μm.

公开(公告)号：US20180235090A1

公开(公告)日：2018-08-16

申请号：US15751218

申请日：2016-08-10

申请人： HITACHI CHEMICAL COMPANY, LTD.

发明人： Hitoshi ONOZEKI ,  Tsubasa INOUE ,  Katsuji YAMAGISHI ,  Hiroshi SHIMIZU

IPC分类号： H05K3/38 ,  H05K3/46 ,  H05K3/06 ,  H05K3/18 ,  H05K3/00 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  C09J163/00

CPC分类号： H05K3/386 ,  C09J163/00 ,  G03F7/038 ,  G03F7/16 ,  G03F7/2002 ,  G03F7/26 ,  H05K1/115 ,  H05K3/0035 ,  H05K3/007 ,  H05K3/061 ,  H05K3/188 ,  H05K3/429 ,  H05K3/4644 ,  H05K3/4652 ,  H05K3/4673 ,  H05K3/4682 ,  H05K2203/0562 ,  H05K2203/0723

摘要： Disclosed is a production method of a multi-layered printed wiring board, including the following steps 1 to 3: Step 1: a step of laminating, on a substrate with inner layer circuit, a metal foil with adhesive layer including a support, a metal foil having a thickness of 3 μm or less and ⅙ or less relative to the thickness of the inner layer circuit, and an organic adhesive layer having a thickness of 10 μm or less in this order, via an organic insulating resin layer such that the organic insulating resin layer and the organic adhesive layer are opposed to each other, and then releasing the support to form a laminated sheet (a) having the metal foil as an outer layer metal foil layer; Step 2: a step of irradiating the laminated sheet (a) with a laser to bore the outer layer metal foil layer, the organic adhesive layer, and the organic insulating resin layer to form a bored laminated sheet (b) having a blind via hole; and Step 3: a step of forming an outer layer circuit connected with the inner layer circuit through the following steps 3-1 to 3-4: Step 3-1: a step of etching removing the outer layer metal foil layer of the bored laminated sheet (b) formed in the step 2 and then forming an outer layer copper layer having a thickness of 2 μm or less on the bored laminated sheet (b); Step 3-2: a step of forming a resist pattern by a resist applied on the outer layer copper layer; Step 3-3: a step of forming a circuit layer on the surface of the outer layer copper layer on which the resist pattern is not formed, by electrolytic copper plating; and Step 3-4: a step of removing the resist pattern and then removing the exposed outer layer copper layer by etching, thereby forming an outer layer circuit connected with the inner layer circuit.

公开(公告)号：US20180063965A1

公开(公告)日：2018-03-01

申请号：US15689348

申请日：2017-08-29

申请人： AT & S Austria Technologie & Systemtechnik Aktieng

发明人： Markus Leitgeb ,  Gernot Grober

IPC分类号： H05K3/32 ,  H01L33/62 ,  H01L33/58 ,  H01L33/48 ,  H05K1/02

CPC分类号： H05K3/321 ,  H01L33/486 ,  H01L33/58 ,  H01L33/62 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/15787 ,  H05K1/0203 ,  H05K1/185 ,  H05K3/0035 ,  H05K3/4697

摘要： A method of supplying a medium into a cavity of a component carrier or a preform of a component carrier, wherein the method comprises providing the component carrier or the preform of the component carrier with the cavity having a slanted sidewall, providing a medium supply device with a tapering portion and a medium supply opening, and optionally supplying the medium into the cavity while the slanted sidewall and the tapering portion are in alignment with one another.

公开(公告)号：US09756732B2

公开(公告)日：2017-09-05

申请号：US14760982

申请日：2013-01-18

申请人： MEIKO ELECTRONICS CO., LTD.

发明人： Yasuaki Seki ,  Tomoyuki Nagata ,  Mitsuaki Toda

IPC分类号： H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H05K3/00 ,  H01L23/00 ,  H01L23/522 ,  H05K3/30 ,  H05K3/46

CPC分类号： H05K1/186 ,  H01L23/5226 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/92144 ,  H05K1/0206 ,  H05K1/0222 ,  H05K1/0298 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K1/185 ,  H05K1/188 ,  H05K3/0017 ,  H05K3/0035 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09827 ,  H05K2201/10 ,  H05K2203/063 ,  H05K2203/1461 ,  Y10T156/10

摘要： A device embedded substrate (20), includes: an insulation layer (12) including an insulation resin material; an electric or electronic device (4) embedded in the insulation layer (12); a terminal (15) serving as an electrode included in the device (4); a conductor pattern (18) formed on the surface of the insulation layer (12); and a conducting via (21) for electrically connecting the conductor pattern (18) and the terminals (15) with each other. The conducting via (21) is made up of a large-diameter section (21a) having a large diameter and a small-diameter section (21b) having a smaller diameter than that of the large-diameter section (21a), in order starting from the conductor pattern (18) toward the terminal (15). A stepped section (17) is formed between the large-diameter section (21a) and the small-diameter section (21b). The large-diameter section (21a) is formed so as to penetrate a sheet-shaped glass cloth (11) disposed in the insulation layer (12).

公开(公告)号：US09648759B2

公开(公告)日：2017-05-09

申请号：US15027784

申请日：2014-09-24

申请人： HITACHI CHEMICAL COMPANY, LTD.

发明人： Nobuyuki Yoshida

IPC分类号： H05K1/09 ,  H05K3/46 ,  H05K3/42 ,  H05K3/00

CPC分类号： H05K3/4652 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/421 ,  H05K3/422

摘要： The present invention is a multilayer wiring board and a method for manufacturing the same, the multilayer wiring board having a hole for interlayer connection penetrating a metal foil and an insulating layer; an overhang of the metal foil formed at an opening of the hole; lower space formed between the overhang and an inside wall of the hole; and interlayer connection in which the hole is filled with electrolytic filling plating layers, wherein the electrolytic filling plating layers are formed as at least two or more layers, the lower space is filled with any electrolytic filling plating layer except for an outermost layer of the two or more layers of electrolytic filling plating layers, and a diameter in the inside of the interlayer connection formed by any electrolytic filling plating layer except for an outermost layer is equal to or larger than a diameter of the opening.

公开(公告)号：US20170064810A1

公开(公告)日：2017-03-02

申请号：US15141149

申请日：2016-04-28

申请人： Research Triangle Institute

发明人： Jay Lewis ,  Dorota Temple ,  Erik Vick ,  Ethan Klem

IPC分类号： H05K1/02 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H05K1/18 ,  H05K3/30

CPC分类号： H05K1/028 ,  H05K1/0206 ,  H05K1/0224 ,  H05K1/115 ,  H05K1/185 ,  H05K1/186 ,  H05K1/189 ,  H05K3/0035 ,  H05K3/284 ,  H05K3/301 ,  H05K3/4038 ,  H05K3/4602 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2203/025

摘要： A flexible electronic assembly includes a flexible current-carrying device, an electrically insulating flexible substrate, and an electronic device embedded in the substrate. The electronic device is mounted face-down on the current-carrying device such that a contact side or component side of the electronic device faces the current-carrying device and is positioned at an interface between the current-carrying device and the substrate. The current-carrying device, substrate, and electronic device are co-planar at the interface. This configuration enables the flexible electronic assembly to have an ultra-thin thickness, for example on the order of micrometers.

摘要翻译： 柔性电子组件包括柔性载流装置，电绝缘柔性基板和嵌入基板中的电子装置。 电子装置面向下安装在载流装置上，使得电子装置的接触侧或部件侧面向载流装置并且位于载流装置和基板之间的界面处。 载流装置，基板和电子装置在界面处是共面的。 该配置使得柔性电子组件具有超薄的厚度，例如几微米的数量级。

公开(公告)号：US09578742B1

公开(公告)日：2017-02-21

申请号：US14821819

申请日：2015-08-10

申请人： Unimicron Technology Corp.

发明人： Shih-Liang Cheng ,  Dyi-Chung Hu ,  Yu-Hua Chen

IPC分类号： H05K1/11 ,  H05K3/00 ,  H05K1/02 ,  H05K3/40 ,  H05K1/09 ,  H05K1/18

CPC分类号： H05K1/11 ,  H05K1/0298 ,  H05K1/182 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/007 ,  H05K3/0097 ,  H05K3/045 ,  H05K3/107 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0195 ,  H05K2203/025 ,  H05K2203/107 ,  H05K2203/1476

摘要： A method for manufacturing a circuit board structure is provided. First, a first circuit layer is formed on a carrier. Then, a first dielectric layer is formed on the carrier and the first circuit layer. Thereafter, at least one first hole is formed in the first dielectric layer to expose a portion of the first circuit layer. Then, a second dielectric layer is formed on the first dielectric layer and the first circuit layer. Thereafter, at least one trench and at least one second hole are formed in the second dielectric layer, in which the trench exposes a portion of the first dielectric layer, and the second hole exposes the portion of the first circuit layer. The second hole is disposed in the first hole. Then, a metal layer is formed to fill the trench and the second hole.

摘要翻译： 提供一种制造电路板结构的方法。 首先，在载体上形成第一电路层。 然后，在载体和第一电路层上形成第一电介质层。 此后，在第一电介质层中形成至少一个第一孔以暴露第一电路层的一部分。 然后，在第一电介质层和第一电路层上形成第二电介质层。 此后，在第二电介质层中形成至少一个沟槽和至少一个第二孔，其中沟槽露出第一电介质层的一部分，并且第二孔露出第一电路层的部分。 第二孔设置在第一孔中。 然后，形成金属层以填充沟槽和第二孔。

公开(公告)号：US09538664B2

公开(公告)日：2017-01-03

申请号：US14104282

申请日：2013-12-12

申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.

发明人： Hiroharu Yanagisawa ,  Kentaro Kaneko ,  Kazuhiro Oshima ,  Junichi Nakamura

IPC分类号： H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K1/03 ,  H05K3/34 ,  H05K3/40 ,  H05K3/46

CPC分类号： H05K3/0035 ,  H05K1/0366 ,  H05K3/0038 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/421 ,  H05K3/427 ,  H05K3/4652 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2203/0346

摘要： A wiring substrate includes a first wiring layer with a wiring pattern and a metal foil. A first insulating layer includes a first through hole having a first end facing the metal foil and a second end. A second wiring layer includes a first opening having a diameter smaller than the second end. A second insulating layer includes a second through hole having a third end facing the wiring pattern and a fourth end. A third wiring layer includes a second opening having a diameter smaller than the fourth end. A first via is filled in the first opening, the first through hole, and a first recess, in the metal foil, having a diameter greater than the first end. A second via is filled in the second opening, the second through hole, and a second recess, in the wiring pattern, having a diameter greater than the third end.

摘要翻译： 布线基板包括具有布线图案的第一布线层和金属箔。 第一绝缘层包括具有面向金属箔的第一端和第二端的第一通孔。 第二布线层包括直径小于第二端的第一开口。 第二绝缘层包括具有面向布线图案的第三端和第四端的第二通孔。 第三布线层包括直径小于第四端的第二开口。 第一通孔被填充在金属箔中的第一开口，第一通孔和第一凹部中，其具有大于第一端的直径。 第二通孔填充在布线图案中的第二开口，第二通孔和第二凹槽中，其直径大于第三端。

公开(公告)号：US20160353585A1

公开(公告)日：2016-12-01

申请号：US15236794

申请日：2016-08-15

申请人： Marvell World Trade Ltd.

发明人： Huahung Kao ,  Shiann-Ming Liou

IPC分类号： H05K3/46 ,  H05K3/10 ,  H05K3/00 ,  H05K3/40

CPC分类号： H05K3/4611 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/0026 ,  H05K3/0035 ,  H05K3/10 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/4655 ,  H05K2201/09518 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2203/107 ,  Y10T156/1057 ,  H01L2924/00

摘要： Embodiments include a multi-layer apparatus comprising a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer, wherein one or more of the dielectric layers include metal layers. The multi-layer apparatus further comprises a first via coupling a first metal layer and a second metal layer, a second via coupling the second metal layer and a fourth metal layer, a third via coupling the first metal layer and the second metal layer, and a fourth via coupling the third metal layer and the fourth metal layer. The first via is contiguous with the second via and the third via is contiguous with the fourth via. At least some of the vias have different depths relative to one another.