公开(公告)号：US20240234503A1

公开(公告)日：2024-07-11

申请号：US18465110

申请日：2023-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOOJIN JEONG ,  Myung Gil Kang ,  Beomjim Park ,  Dongwon KIm ,  Younggwon Kim ,  Hyumin Yoo

IPC: H01L29/06 ,  H01L23/48 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L23/481 ,  H01L27/092 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate including first and second active regions, a first active pattern on the first active region, a second active pattern on the second active region, a device isolation layer filling a trench between the first active pattern and the second active pattern, the device isolation layer having a concave top surface, a first gate electrode in the first active region, a second gate electrode in the second active region, a gate cutting pattern disposed between the first gate electrode and the second gate electrode and separating the first gate electrode and the second gate electrode, and an insulating pattern between the gate cutting pattern and the concave top surface of the device isolation layer.

公开(公告)号：US20250015157A1

公开(公告)日：2025-01-09

申请号：US18599943

申请日：2024-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomjin Park ,  Myung Gil Kang ,  Dongwon Kim ,  Younggwon Kim ,  Jongsu Kim ,  Hyumin Yoo ,  Soojin Jeong

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

Abstract: The present disclosure relates to semiconductor devices and their fabrication methods. An example semiconductor device comprises a substrate including an active pattern, a channel pattern including semiconductor patterns, a source/drain pattern connected to the semiconductor patterns, an inner gate electrode between two neighboring semiconductor patterns, an inner gate dielectric layer, and an inner high-k dielectric layer between the inner gate electrode and the inner gate dielectric layer. The inner gate dielectric layer includes an upper dielectric layer, a lower dielectric layer, and an inner spacer. A first thickness of the inner spacer is greater than a second thickness of the upper or lower dielectric layer. The first thickness is greater than a third thickness of the inner high-k dielectric layer.