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公开(公告)号:US20240321961A1
公开(公告)日:2024-09-26
申请号:US18613338
申请日:2024-03-22
发明人: Jongsu Kim , Myunggil Kang , Dongwon Kim , Beomjin Park , Inhyun Song , Hyumin Yoo , Yujin Jeon
IPC分类号: H01L29/06 , H01L27/092 , H01L29/08 , H01L29/423 , H01L29/775 , H01L29/786
CPC分类号: H01L29/0673 , H01L27/092 , H01L29/0847 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要: An integrated circuit device includes, a first nano-sheet stack including a plurality of nano-sheets arranged on a fin-type active region extending in a first horizontal direction, a gate line extending in a second horizontal direction on the fin-type active region, a vertical structure contacting the plurality of nano-sheets, and a first gate dielectric layer disposed between the gate line and the plurality of nano-sheets and between the gate line and the vertical structure, wherein the gate line includes a first sub-gate portion disposed under each of the plurality of nano-sheets, the first gate dielectric layer includes a first portion disposed between the gate line and the plurality of nano-sheets, and a second portion disposed between the first sub-gate portion and the vertical structure, and a thickness of the second portion in the second horizontal direction is greater than a thickness of the first portion in the vertical direction.
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公开(公告)号:US20240321956A1
公开(公告)日:2024-09-26
申请号:US18614804
申请日:2024-03-25
发明人: Woosuk Choi , Beomjin Park , Myunggil Kang , Dongwon Kim , Hyumin Yoo , Soojin Jeong
IPC分类号: H01L29/06 , H01L27/088 , H01L29/08 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号: H01L29/0665 , H01L27/088 , H01L29/0847 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66553 , H01L29/775 , H01L29/78696
摘要: An integrated circuit device includes a fin-type active region that protrudes from a substrate and extends in a first horizontal direction, a plurality of nanosheets disposed on the fin-type active region and separated from each other in the vertical direction, a gate line that extends in a second horizontal direction and that surrounds the plurality of nanosheets on the fin-type active region, and includes respective sub-gate portions between the plurality of nanosheets and a main gate portion above the uppermost layer of the plurality of nanosheets, a source/drain region disposed on the fin-type active region, adjacent to the gate line, and connected to the plurality of nanosheets, and a plurality of inner spacers interposed between the gate line and the source/drain region. The shapes of first inner spacers that face the sub-gate portions differ from the shape of a second inner spacer that faces the main gate portion.
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公开(公告)号:US20240234503A1
公开(公告)日:2024-07-11
申请号:US18465110
申请日:2023-09-11
发明人: SOOJIN JEONG , Myung Gil Kang , Beomjim Park , Dongwon KIm , Younggwon Kim , Hyumin Yoo
IPC分类号: H01L29/06 , H01L23/48 , H01L27/092 , H01L29/417 , H01L29/423 , H01L29/775 , H01L29/786
CPC分类号: H01L29/0673 , H01L23/481 , H01L27/092 , H01L29/41733 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要: A semiconductor device includes a substrate including first and second active regions, a first active pattern on the first active region, a second active pattern on the second active region, a device isolation layer filling a trench between the first active pattern and the second active pattern, the device isolation layer having a concave top surface, a first gate electrode in the first active region, a second gate electrode in the second active region, a gate cutting pattern disposed between the first gate electrode and the second gate electrode and separating the first gate electrode and the second gate electrode, and an insulating pattern between the gate cutting pattern and the concave top surface of the device isolation layer.
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公开(公告)号:US20240079466A1
公开(公告)日:2024-03-07
申请号:US18136975
申请日:2023-04-20
发明人: Sangwon Baek , Beomjin Park , Myung Gil Kang , Dongwon Kim , Hyumin Yoo , Namkyu Cho
IPC分类号: H01L29/423 , H01L21/8238 , H01L27/092 , H01L29/66 , H01L29/775
CPC分类号: H01L29/42392 , H01L21/823814 , H01L27/092 , H01L29/66439 , H01L29/66742 , H01L29/775 , H01L2029/42388
摘要: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns spaced apart from each other, a source/drain pattern connected to the plurality of semiconductor patterns, a gate electrode including, an inner electrode between a first semiconductor pattern of the plurality of semiconductor patterns and a second semiconductor pattern of the plurality of semiconductor patterns, the first semiconductor pattern and the second semiconductor pattern being adjacent to each other, and an outer electrode on an uppermost semiconductor pattern of the plurality of semiconductor patterns.
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