公开(公告)号：US20240321831A1

公开(公告)日：2024-09-26

申请号：US18606534

申请日：2024-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Insup SHIN ,  Hyeongmun KANG ,  Yuduk KIM ,  Seungwoo SIM

IPC: H01L25/065 ,  H01L23/00 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/05012 ,  H01L2224/06131 ,  H01L2224/16148 ,  H01L2224/32148 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2924/1436 ,  H10B80/00

Abstract: Provided is a semiconductor package including a first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, a plurality of conductive front pads on lower surfaces of the plurality of second semiconductor chips, a plurality of conductive rear pads attached to an upper surface of the first semiconductor chip and an upper surface of each of the plurality of second semiconductor chips, and including a plurality of first bonding pads and a plurality of second bonding pads in different regions, and a plurality of chip connection terminals between the plurality of conductive front pads and the plurality of conductive rear pads, wherein each of the plurality of second bonding pads includes a supporting part configured to support each of the plurality of chip connection terminals, and a fixing part protruding from an upper surface of the supporting part.

公开(公告)号：US20240088108A1

公开(公告)日：2024-03-14

申请号：US18202375

申请日：2023-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonghyun BAEK ,  Yuduk KIM ,  Hyunsoo CHUNG

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L23/49827 ,  H01L24/09 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0903 ,  H01L2224/16148 ,  H01L2224/16157 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2924/2064

Abstract: A semiconductor package includes: a base chip; semiconductor chips disposed on the base chip and including front pads disposed on a front surface opposing the base chip, rear pads disposed on a rear surface opposing the front surface, and through-vias; bumps disposed between the semiconductor chips; a dam structure disposed on at least a portion of the rear pads; and insulating adhesive layers at least partially surrounding the bumps and the dam structure, wherein the rear pads include first pads that are disposed in a center region that crosses a center of the rear surface and that are electrically connected to the through-vias, and second pads that are disposed in a peripheral region adjacent to the center region, wherein the second pads include a line pad of which at least a portion has a polygonal shape, and wherein the dam structure has a bent shape.