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公开(公告)号：US20240153856A1
公开(公告)日：2024-05-09
申请号：US18386003
申请日：2023-11-01
发明人： Joonghyun BAEK , Hyunsoo CHUNG , Dongok KWAK , Eunjeong IM
IPC分类号： H01L23/498 , H01L23/00 , H01L23/31 , H01L25/10 , H10B80/00
CPC分类号： H01L23/49822 , H01L23/3107 , H01L23/49816 , H01L23/49838 , H01L24/16 , H01L24/73 , H01L25/105 , H10B80/00 , H01L24/32 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/1431 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/1441 , H01L2924/15174 , H01L2924/15184 , H01L2924/15311
摘要： A semiconductor package having a lower redistribution structure includes a redistribution insulation layer, a plurality of ball pads in the redistribution insulation layer apart from one another, a double via which includes a first active via and a dummy via located on at least one of the plurality of ball pads and apart from each other in the redistribution insulation layer, and a first active redistribution layer electrically connected to the first active via in the redistribution insulation layer, solder balls electrically connected to the plurality of ball pads under the lower redistribution structure, a first semiconductor chip on the lower redistribution structure and electrically connected to the first active via and the first active redistribution layer of the lower redistribution structure, and a molding layer molding the first semiconductor chip on the lower redistribution structure.
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公开(公告)号：US20240071997A1
公开(公告)日：2024-02-29
申请号：US18308358
申请日：2023-04-27
发明人： Joonghyun BAEK , In LEE
IPC分类号： H01L25/065 , H01L23/00 , H01L23/498 , H01L23/538 , H10B80/00
CPC分类号： H01L25/0652 , H01L23/49816 , H01L23/49833 , H01L23/5385 , H01L23/5386 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H10B80/00 , H01L2224/32145 , H01L2224/32225 , H01L2224/48139 , H01L2224/48147 , H01L2224/48227 , H01L2224/4917 , H01L2224/49176 , H01L2224/49177 , H01L2224/73215 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2924/1431 , H01L2924/1436 , H01L2924/1438
摘要： A semiconductor package includes: a substrate that includes a wiring circuit; an interposer on the substrate, wherein the interposer includes a first side and a second side opposing each other and a third side and a fourth side between the first side and the second side, and wherein the interposer includes an interconnect circuit electrically connected to the wiring circuit; a first and second buffer chips on the interposer; a first chip stack adjacent to the first side of the interposer and connected to the first buffer chip; a second chip stack adjacent to the second side of the interposer and connected to the second buffer chip; a third chip stack adjacent to the third side of the interposer, and wherein the third chip stack includes first and second groups of semiconductor chips, which are electrically connected to the first and second buffer chips, respectively, via the interconnect circuit.
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公开(公告)号：US20240179925A1
公开(公告)日：2024-05-30
申请号：US18453611
申请日：2023-08-22
发明人： Jaekyu SUNG , Joonghyun BAEK , Cheolwoo LEE
CPC分类号： H10B80/00 , H01L24/06 , H01L24/48 , H01L24/49 , H01L25/18 , H01L23/3128 , H01L2224/06135 , H01L2224/48091 , H01L2224/48106 , H01L2224/48145 , H01L2224/48227 , H01L2224/4903 , H01L2224/49175
摘要： A semiconductor package may include a substrate; at least one controller chip on the substrate; at least one chip structure on the substrate, the at least one chip structure including a buffer chip, an upper chip stack on the buffer chip, and a lower chip stack below the buffer chip; an upper wire electrically connecting the upper chip stack, the buffer chip, and the at least one controller chip; a lower wire electrically connecting the lower chip stack and the at least one controller chip; a connection wire electrically connecting the at least one controller chip to the substrate; and connection bumps below the substrate, the connection bumps being electrically connected to the at least one controller chip and the at least one chip structure.
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公开(公告)号：US20240250066A1
公开(公告)日：2024-07-25
申请号：US18535339
申请日：2023-12-11
发明人： Joonghyun BAEK , Hyungu KANG , Cheol-Woo LEE , Sunghwan YOON , Eunjeong IM
IPC分类号： H01L25/065 , H01L23/00 , H01L23/31 , H01L23/538 , H01L25/10
CPC分类号： H01L25/0652 , H01L23/3128 , H01L23/5381 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48227 , H01L2224/73215 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562
摘要： A semiconductor package including first and second chip stacks each including semiconductor chips having an offset stack structure, the second chip stack horizontally spaced apart from the first chip stack, a first buffer chip on the substrate and at a side of the first chip stack, a second buffer chip on the substrate and at a side of the second chip stack, a connection substrate on the first and second chip stacks, a first mold layer covering the substrate, the first chip stack, and the second stack and exposing a top surface of the connection substrate, third and fourth chip stacks each including semiconductor chips having an offset stack structure on the first mold layer and, the fourth chip stack horizontally spaced apart from the third chip stack, and a second mold layer covering the first mold layer, the third chip stack, and the fourth chip stack may be provided.
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公开(公告)号：US20240088108A1
公开(公告)日：2024-03-14
申请号：US18202375
申请日：2023-05-26
发明人： Joonghyun BAEK , Yuduk KIM , Hyunsoo CHUNG
IPC分类号： H01L25/10 , H01L23/00 , H01L23/498
CPC分类号： H01L25/105 , H01L23/49827 , H01L24/09 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/0903 , H01L2224/16148 , H01L2224/16157 , H01L2224/26145 , H01L2224/32145 , H01L2224/73204 , H01L2924/2064
摘要： A semiconductor package includes: a base chip; semiconductor chips disposed on the base chip and including front pads disposed on a front surface opposing the base chip, rear pads disposed on a rear surface opposing the front surface, and through-vias; bumps disposed between the semiconductor chips; a dam structure disposed on at least a portion of the rear pads; and insulating adhesive layers at least partially surrounding the bumps and the dam structure, wherein the rear pads include first pads that are disposed in a center region that crosses a center of the rear surface and that are electrically connected to the through-vias, and second pads that are disposed in a peripheral region adjacent to the center region, wherein the second pads include a line pad of which at least a portion has a polygonal shape, and wherein the dam structure has a bent shape.
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公开(公告)号：US20240079380A1
公开(公告)日：2024-03-07
申请号：US18334062
申请日：2023-06-13
发明人： Joonghyun BAEK , Jaekyu SUNG , Dongok KWAK , Taeyoung LEE
IPC分类号： H01L25/065 , H01L23/00
CPC分类号： H01L25/0657 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L2224/32145 , H01L2224/48147 , H01L2224/48227 , H01L2224/73215 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562
摘要： A stacked semiconductor package may include a package base substrate, a first chip stack including a first semiconductor chips stacked sequentially on the package base substrate, a second chip stack including second semiconductor chips stacked sequentially on the first chip stack, and bonding wires electrically connecting the first semiconductor chips and the second semiconductor chips to the package base substrate. Each of the first semiconductor chips may be shifted by a first interval in a first horizontal direction to have a step shape. Each of the second semiconductor chips may be shifted by the first interval in a second horizontal direction, opposite to the first horizontal direction, to have a step shape. A lowermost second semiconductor chip may be shifted from an uppermost first semiconductor chip by a second interval in the second direction. The second interval may be greater than the first interval.
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