公开(公告)号：US20230260568A1

公开(公告)日：2023-08-17

申请号：US18303309

申请日：2023-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinseok KIM ,  Yulhwa KIM ,  Jae-Joon KIM ,  Hyungjun KIM

IPC: G11C11/412 ,  G06N3/08 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C11/412 ,  G06N3/08 ,  G11C11/418 ,  G11C11/419

Abstract: Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

公开(公告)号：US20200184315A1

公开(公告)日：2020-06-11

申请号：US16561378

申请日：2019-09-05

Applicant: Samsung Electronics Co., Ltd. ,  POSTECH ACADEMY-INDUSTRY FOUNDATION

Inventor： Sungho KIM ,  Yulhwa KIM ,  Hyungjun KIM ,  Jae-Joon KIM ,  Jinseok KIM

IPC: G06N3/04 ,  G06N3/08

Abstract: A method of implementing a neural network in a neuromorphic apparatus having a memory and processing circuitry, where the method includes dividing, by the processing circuitry, the neural network into a plurality of sub-networks based on a size of a core of the memory to implement the neural network, initializing, by the processing circuitry, a hyper-parameter used in the sub-networks, and training, by the processing circuitry, the sub-networks by using the hyper-parameter.

公开(公告)号：US20250014638A1

公开(公告)日：2025-01-09

申请号：US18891682

申请日：2024-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinseok KIM ,  Yulhwa KIM ,  Jae-Joon KIM ,  Hyungjun KIM

IPC: G11C11/412 ,  G06N3/08 ,  G11C11/418 ,  G11C11/419

Abstract: Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

公开(公告)号：US20230153594A1

公开(公告)日：2023-05-18

申请号：US18094351

申请日：2023-01-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Joon KIM ,  Hyungjun KIM ,  Yulhwa KIM

IPC: G06N3/063 ,  G11C11/54 ,  G06N3/04 ,  G11C13/00

CPC classification number: G06N3/063 ,  G11C11/54 ,  G06N3/04 ,  G11C13/0069 ,  G11C13/004

Abstract: Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.

公开(公告)号：US20190138892A1

公开(公告)日：2019-05-09

申请号：US16170081

申请日：2018-10-25

Applicant: Samsung Electronics Co., Ltd. ,  Postech Academy-Industry Foundation

Inventor： Sungho KIM ,  Jinseok KIM ,  Yulhwa KIM ,  Jaejoon KIM ,  Dusik PARK

IPC: G06N3/063 ,  G06N3/04

Abstract: A method of performing operations on a plurality of inputs and a same kernel using a delay time by using a same processor, and a neural network device thereof are provided, the neural network device includes input data including a first input and a second input, and a processor configured to obtain a first result by performing operations between the first input and a plurality of kernels, to obtain a second result by performing operations between the second input, which is received at a time delayed by a first interval from a time when the first input is received, and the plurality of kernels, and to obtain output data using the first result and the second result. The neural network device may include neuromorphic hardware and may perform convolutional neural network (CNN) mapping.