公开(公告)号：US20250061262A1

公开(公告)日：2025-02-20

申请号：US18935822

申请日：2024-11-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonnyung LEE ,  Yeongjun KWON ,  Jaeyong SHIN ,  Jeonghoon AHN ,  Yunki CHOI

IPC: G06F30/3953 ,  H01L23/528

Abstract: A method of designing an interconnect structure of a semiconductor apparatus is provided. The interconnect structure includes interconnection layers sequentially stacked on a semiconductor substrate, and each of the interconnection includes dummy metal patterns and main metal patterns. The method includes: determining a layout of the main metal patterns included in each of the plurality of interconnection layers; determining a number of interconnection layers in the plurality of interconnection layers; and determining a layout of the dummy metal patterns included in each of the plurality of interconnection layers based on the determined layout of the main metal patterns and the determined number of interconnection layers.

公开(公告)号：US20240395672A1

公开(公告)日：2024-11-28

申请号：US18792962

申请日：2024-08-02

Applicant: Name SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Shaofeng DING ,  Sungwook MOON ,  Jeonghoon AHN ,  Yunki CHOI

IPC: H01L23/48 ,  H01L23/522 ,  H01L25/065

Abstract: A semiconductor chip may include; a device layer including transistors on a substrate, a wiring layer on the device layer, a first through via passing through the device layer and the substrate, and a second through via passing through the wiring layer, the device layer and the substrate, wherein a first height of the first through via is less than a second height of the second through via.

公开(公告)号：US20240071924A1

公开(公告)日：2024-02-29

申请号：US18232894

申请日：2023-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungil PARK ,  Jeonghoon AHN ,  Yunki CHOI

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76807 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/53295 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76883 ,  H01L2221/1036

Abstract: An integrated circuit device includes an interconnection structure that includes: an interlayer insulating layer arranged on a substrate and having a plurality of trenches; a first conductive layer formed inside a first trench of the plurality of trenches; a second conductive layer formed inside a second trench of the plurality of trenches, wherein the second trench is spaced apart from the first trench; a third conductive layer formed inside a third trench of the plurality of trenches, wherein the third trench is spaced apart from the second trench; and a dielectric layer formed between the first conductive layer and the second conductive layer, wherein a portion of interlayer insulating layer is disposed between the second conductive layer and the third conductive layer, and wherein a first width of the first conductive layer is greater than a second width of the second conductive layer.