-
公开(公告)号：US20220223543A1
公开(公告)日：2022-07-14
申请号：US17705770
申请日：2022-03-28
发明人： Eunkyoung CHOI , Suchang LEE , Yunseok CHOI
IPC分类号： H01L23/00 , H01L23/16 , H01L23/498 , H01L25/065 , H01L25/18
摘要： A semiconductor package having a stiffening structure is disclosed. The semiconductor package includes a substrate, an interposer on the substrate, and a first logic chip, a second logic chip, memory stacks and stiffening chips, all of which are on the interposer. The first logic chip and the second logic chip are adjacent to each other. Each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip. Each memory stack includes a plurality of stacked memory chips. Each stiffening chip is disposed between corresponding ones of the memory stacks, to be aligned and overlap with a boundary area between the first logic chip and the second logic chip.
-
公开(公告)号：US20220368927A1
公开(公告)日：2022-11-17
申请号：US17877539
申请日：2022-07-29
发明人： Wonseok LEE , Yunseok CHOI
IPC分类号： H04N19/182 , H04N19/46 , H04N19/105 , H04N19/136
摘要： An image encoder configured to process a Bayer image generated by passing through a color filter of a Bayer pattern includes: a detector configured to read the Bayer image in units of blocks and search for, in the blocks, a target pixel to be compressed and a plurality of candidate pixels which are located adjacent to the target pixel; a flag generator configured to compare a first pixel value of the target pixel with second pixel values based on pixel values of the plurality of candidate pixels, identify a reference pixel based on a comparison result, and generate a flag indicating relative direction information between the target pixel and the reference pixel; and a compressor configured to encode information corresponding to a comparison method applied by the flag generator and the comparison result and output the encoded information as a bitstream together with the flag.
-
公开(公告)号：US20220122219A1
公开(公告)日：2022-04-21
申请号：US17350003
申请日：2021-06-17
发明人： JEONGGUK LEE , Yunseok CHOI
摘要： An electronic device, method thereof, and digital camera are provided, including an image sensor that generates pixel data based on light received through a lens that permits distortion where a captured image is compressed in a first direction, and an image signal processor that performs re-mosaic processing on the pixel data for correcting distortion occurring in the first direction and to generate re-mosaiced pixel data.
-
公开(公告)号：US20210337240A1
公开(公告)日：2021-10-28
申请号：US17236458
申请日：2021-04-21
发明人： Wonseok LEE , Seongwook SONG , Yunseok CHOI
IPC分类号： H04N19/85 , H04N19/182 , H04N19/186 , H04N19/184 , H04N19/42
摘要： A camera module includes a compressor configured to divide a plurality of pixels included in image data, into a plurality of pixel groups, with respect to each of the plurality of pixel groups into which the plurality of pixels is divided, calculate a representative pixel value of a corresponding pixel group, based on pixel values of multiple pixels included in the corresponding pixel group, generate first compressed data, based on the calculated representative pixel value of each of the plurality of pixel groups, with respect to each of the plurality of pixel groups into which the plurality of pixels is divided, calculate residual values representing differences between the pixel values of the multiple pixels included in the corresponding pixel group and the representative pixel value of the corresponding pixel group, and generate second compressed data, based on the calculated residual values of each of the plurality of pixel groups.
-
公开(公告)号：US20220020181A1
公开(公告)日：2022-01-20
申请号：US17374426
申请日：2021-07-13
发明人： Wonseok LEE , Seongwook SONG , Yunseok CHOI
IPC分类号： G06T9/00 , G06T3/40 , H04N19/105 , H04N19/182 , H04N19/186 , H04N19/176
摘要： Provided are an image sensor module, an image processing system, and an image compression method. The image compression method of compressing image data generated by an image sensor includes: receiving pixel values of a target pixel group of image data on which compression is to be performed, and reference values of reference pixels to be used in compression of the target pixel group; determining an averaging direction in which an averaging calculation is to be performed on target pixel values; averaging the pixel values of target pixels in the averaging direction; generating balance information including compensation values to be applied to the average values based on the reference pixels; and generating a bitstream based on the average values, the balance information, and compression information.
-
公开(公告)号：US20210391269A1
公开(公告)日：2021-12-16
申请号：US17163988
申请日：2021-02-01
发明人： Yukyung PARK , Minseung YOON , Yunseok CHOI
IPC分类号： H01L23/538 , H01L23/498 , H01L23/367
摘要： An interposer includes a base layer including a first surface and a second surface that are opposite to each other. An interconnect structure is disposed on the first surface. The interconnect structure includes a metal interconnect pattern and an insulating layer surrounding the metal interconnect pattern. A first lower protection layer is disposed on the second surface. A plurality of lower conductive pads is disposed on the first lower protection layer. A plurality of through electrodes penetrates the base layer and the first lower protection layer. The plurality of through electrodes electrically connects the metal interconnect pattern of the interconnect structure to the lower conductive pads. At least one of the insulating layer and the first lower protection layer has compressive stress. A thickness of the first lower protection layer is in a range of about 13% to about 30% of a thickness of the insulating layer.
-
公开(公告)号：US20210151388A1
公开(公告)日：2021-05-20
申请号：US16848106
申请日：2020-04-14
发明人： Eunkyoung CHOI , Suchang LEE , Yunseok CHOI
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18 , H01L23/16 , H01L23/498
摘要： A semiconductor package having a stiffening structure is disclosed. The semiconductor package includes a substrate, an interposer on the substrate, and a first logic chip, a second logic chip, memory stacks and stiffening chips, all of which are on the interposer. The first logic chip and the second logic chip are adjacent to each other. Each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip. Each memory stack includes a plurality of stacked memory chips. Each stiffening chip is disposed between corresponding ones of the memory stacks, to be aligned and overlap with a boundary area between the first logic chip and the second logic chip.
-
公开(公告)号：US20210021751A1
公开(公告)日：2021-01-21
申请号：US16923569
申请日：2020-07-08
发明人： Jeongguk LEE , Yunseok CHOI , Dochang AHN , Sunghyuk YIM
IPC分类号： H04N5/235 , H04N5/265 , H04N19/184 , G06T5/50
摘要： An image sensor and an image processing system in which the image sensor includes a sensing unit configured to generate a plurality of images having different luminances with respect to a same object, a pre-processor configured to merge n images (n is a natural number equal to or greater than 2) except for at least one of the plurality of images to generate a merged image, and an interface circuit configured to output the at least one image and the merged image to an external processor.
-
公开(公告)号：US20240096777A1
公开(公告)日：2024-03-21
申请号：US18323646
申请日：2023-05-25
发明人： Jaesun KIM , Sanghyun LEE , Yeonho JANG , Yunseok CHOI
IPC分类号： H01L23/498 , H01L21/66 , H01L23/00 , H01L25/065
CPC分类号： H01L23/49838 , H01L22/12 , H01L22/14 , H01L23/49822 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L2224/16148 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81203 , H01L2224/81815 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/1431 , H01L2924/1432 , H01L2924/1433 , H01L2924/1436 , H01L2924/1437 , H01L2924/14511
摘要： A semiconductor package includes a redistribution structure in which redistribution layers and insulating layers are alternately stacked. A semiconductor chip is electrically connected to the redistribution layers, and bumps are electrically connected to the redistribution layers and arranged on one surface of the redistribution structure. The redistribution layers include pads arranged to face the bumps, and each of the pads includes a first pad portion offset from a center of each of the pads in a first direction, a second pad portion offset from the center of each of the pads in a second direction, and a connection portion connecting the first and second pad portions. The connection portion includes a protruding portion that defines a first recessed region recessed adjacent to the first pad portion and a second recessed region recessed adjacent to the second pad portion.
-
公开(公告)号：US20240006328A1
公开(公告)日：2024-01-04
申请号：US18244350
申请日：2023-09-11
发明人： Yukyung PARK , Minseung YOON , Yunseok CHOI
IPC分类号： H01L23/538 , H01L23/498 , H01L23/367
CPC分类号： H01L23/5386 , H01L23/49838 , H01L23/5383 , H01L23/3675 , H01L23/49822
摘要： An interposer includes a base layer including a first surface and a second surface that are opposite to each other. An interconnect structure is disposed on the first surface. The interconnect structure includes a metal interconnect pattern and an insulating layer surrounding the metal interconnect pattern. A first lower protection layer is disposed on the second surface. A plurality of lower conductive pads is disposed on the first lower protection layer. A plurality of through electrodes penetrates the base layer and the first lower protection layer. The plurality of through electrodes electrically connects the metal interconnect pattern of the interconnect structure to the lower conductive pads. At least one of the insulating layer and the first lower protection layer has compressive stress. A thickness of the first lower protection layer is in a range of about 13% to about 30% of a thickness of the insulating layer.
-
-
-
-
-
-
-
-
-
搜索结果
18 条记录 (耗时 0.018 秒)
