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公开(公告)号：US20190386615A1
公开(公告)日：2019-12-19
申请号：US16268676
申请日：2019-02-06
发明人： Jonghan KIM , Chisung BAE , Jaemin CHOI , Yoonmyung LEE , Jung-Hoon CHUN
IPC分类号： H03B5/24
摘要： An oscillator includes a constant current generator configured to generate a constant current by maintaining a predetermined potential difference between both a first end and a second end of a resistor, and an oscillating element configured to output a clock signal corresponding to a charge and discharge cycle of a capacitor based on a bias current corresponding to the constant current.
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公开(公告)号：US20240232595A1
公开(公告)日：2024-07-11
申请号：US18334516
申请日：2023-06-14
发明人： Jung-Hoon CHUN , Jiho SONG , Yoonmyung LEE , Jua LEE
IPC分类号： G06N3/063
CPC分类号： G06N3/063
摘要： An electronic device with neural network circuitry is provided. The neural network circuit includes a synaptic memory cell including a memory element disposed along an output line and configured to, dependent on the memory element and an input signal applied to an input line, generate a column signal on the output line; a reference memory cell comprising a reference memory element disposed along a reference line, and configured to, dependent on the reference memory element and the input signal, generate a reference signal on the reference line; and a first neuron circuit configured to generate an output signal based on the column signal and the reference signal, and determine a start voltage of an integration to be performed based on the output signal in response to a previous firing by the first neuron circuit with respect to a previous input signal or another firing performed by a second neuron circuit.
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公开(公告)号：US20230186986A1
公开(公告)日：2023-06-15
申请号：US17830004
申请日：2022-06-01
发明人： Jung-Hoon CHUN , Jiho SONG , Yoonmyung LEE , Jua LEE
CPC分类号： G11C13/004 , G11C13/0069 , G11C13/0038 , G11C11/54
摘要： A device with a neural network includes: a synaptic memory cell comprising a resistive memory element, which is disposed along an output line and which has either one of a first resistance value and a second resistance value, and configured to generate a column signal based on the resistive memory element and an input signal in response to the input signal being received through an input line; a reference memory cell comprising a reference memory element, which is disposed along a reference line and which has the second resistance value different from the first resistance value, and configured to generate a reference signal based on the reference memory element and the input signal; and an output circuit configured to generate an output signal for the output line from the column signal and the reference signal.
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公开(公告)号：US20220254383A1
公开(公告)日：2022-08-11
申请号：US17481995
申请日：2021-09-22
发明人： Hyeran KIM , Junyeol LEE , Jung-Hoon CHUN
摘要： An output driver includes a pre driver including pre driving circuits, each including first and second pre pumps, and a main driver including main driving circuits, each including first and second main pumps. Each of the first and second pre pumps includes a first driving capacitor, and each of the first and second main pumps includes a second driving capacitor. During a first half cycle of a clock signal, the first pre pump and the first main pump perform a precharge operation, and the second pre pump and the second main pump perform a first driving operation, and during a second half cycle of the clock signal, the first pre pump and the first main pump perform the first driving operation, and the second pre pump and the second main pump perform the precharge operation. Capacitances of the first and second driving capacitors are different.
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公开(公告)号：US20200184174A1
公开(公告)日：2020-06-11
申请号：US16627006
申请日：2018-04-23
发明人： Kyung-Hoon SONG , Jung-Hoon CHUN
摘要： An electronic device, according to various embodiments of the present invention, may comprise: a pixel array consisting of an arrangement of pixels, each forming a capacitance corresponding to at least a portion of an object; a protective layer disposed on the pixel array; and guide walls formed and arranged within the protective layer, wherein the guide walls have a lower dielectric constant than other portions of the protective layer and may be arranged at an interval corresponding to at least the width of the width or length of each of the pixels. The electronic device as above may vary according to the embodiments.
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公开(公告)号：US20210297107A1
公开(公告)日：2021-09-23
申请号：US17176897
申请日：2021-02-16
发明人： Dongsuk KANG , Xuefan JIN , Jaewoo PARK , Jung-Hoon CHUN , Kyu Dong HWANG , Dae Han KWON
摘要： A transceiver includes a duobinary conversion circuit configured to determine a level of an input signal which is a duobinary signal according to an intermediate voltage, a first reference voltage higher than the intermediate voltage, and a second reference voltage lower than the intermediate voltage, and to convert the input signal into a non-return-to-zero (NRZ) signal; and a control circuit configured to generate one or more control signals to substantially remove inter-symbol interference (ISI) between symbols of the input signal, and to adjust the first reference voltage, or the second reference voltage, or both according to the level of the input signal.
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公开(公告)号：US20220166451A1
公开(公告)日：2022-05-26
申请号：US17412141
申请日：2021-08-25
发明人： Dongsuk KANG , Jaewoo PARK , Jung-Hoon CHUN , Kyu Dong HWANG , Dae Han KWON
摘要： A duobinary receiver includes a signal dividing circuit configured to output a plurality of data by dividing an input signal according to a plurality of multi-phase sampling clocks signals; a level detecting circuit configured to output a plurality of state signals respectively corresponding to duobinary levels of the plurality of data; and a data converting circuit configured to decode the plurality of state signals to output a corresponding plurality of bits.
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公开(公告)号：US20210091922A1
公开(公告)日：2021-03-25
申请号：US16889077
申请日：2020-06-01
发明人： Tae-Jin KIM , Jung-Hoon CHUN , Jae Youl LEE , Hyun Wook LIM
摘要： A signal receiving device may not need to consider jitter characteristics of a received signal by including a transition detecting device which receives first to third input signals having different signal levels for each unit interval, compares whether a signal level of a first differential signal, which is a differential signal between the first input signal and the second input signal among the first to third input signals, is greater than a first reference signal level to output a first comparison signal, and compares whether the signal level of the first differential signal is greater than a second reference signal level different from the first reference signal level to output a second comparison signal, and a clock data recovering device which recovers a clock signal embedded in the first to third input signals on the basis of the first and second comparison signals to output the recovery clock signal.
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