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    Transmitting apparatus and receiving apparatus and controlling method thereof
    2.
    发明授权
    Transmitting apparatus and receiving apparatus and controlling method thereof 有权

    公开(公告)号：US11595169B2

    公开(公告)日：2023-02-28

    申请号：US17092909

    申请日：2020-11-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young-ho Oh ,  Se-ho Myung ,  Hak-ju Lee

    IPC: H04L5/00 ,  H04L27/26

    Abstract: A transmitting apparatus includes: a frame generator configured to generate a frame including a plurality of OFDM symbols; and a signal processor configured to signal-process the generated frame, wherein the plurality of OFDM symbols are included in a bootstrap, a preamble including an L1 basic and an L1 detail, and a payload, and wherein the bootstrap includes information on an FFT size of the OFDM symbols included in the preamble, a length of a guard interval (GI) inserted in the preamble, and a pattern of a preamble pilot inserted in the preamble, and information on an L1 basic mode.

    Transmitting apparatus and signal processing method thereof
    3.
    发明授权
    Transmitting apparatus and signal processing method thereof 有权

    公开(公告)号：US11575393B2

    公开(公告)日：2023-02-07

    申请号：US17329779

    申请日：2021-05-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Se-ho Myung ,  Hong-sil Jeong ,  Kyung-joong Kim

    IPC: H03M13/27 ,  H03M13/11 ,  H03M13/25 ,  H03M13/00 ,  H04L1/00 ,  H04L27/26

    Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver is formed of a plurality of columns each including a plurality of rows and includes a block interleaver configured to divide each of the plurality of columns into a first part and a second part and interleave the LDPC codeword, the number of rows constituting each column divided into the first part is determined differently depending upon the modulation method, wherein the number of rows constituting each column divided into the second part is determined depending upon the number of rows constituting each column divided into the first part.

    Transmitter and shortening method thereof
    5.
    发明授权
    Transmitter and shortening method thereof 有权

    公开(公告)号：US11522560B2

    公开(公告)日：2022-12-06

    申请号：US16777461

    申请日：2020-01-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Se-ho Myung ,  Kyung-joong Kim ,  Hong-sil Jeong

    IPC: H03M13/11 ,  H03M13/00 ,  H03M13/29 ,  H03M13/25 ,  H03M13/15 ,  H04L1/00 ,  H03M13/27

    Abstract: A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to generate a plurality of bit groups each of which is formed of a same number of bits, maps the outer-encoded bits to some of the bits in the bit groups, and pads zero bits to remaining bits in the bit groups, based on a predetermined shortening pattern, thereby to constitute Low Density Parity Check (LDPC) information bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the remaining bits in which zero bits are padded include some of the bit groups which are not sequentially disposed in the LDPC information bits.

    Transmitter and shortening method thereof
    6.
    发明授权
    Transmitter and shortening method thereof 有权

    公开(公告)号：US11223445B2

    公开(公告)日：2022-01-11

    申请号：US16504103

    申请日：2019-07-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hong-sil Jeong ,  Kyung-Joong Kim ,  Se-ho Myung

    IPC: H04L1/00 ,  H03M13/11 ,  H03M13/15 ,  H03M13/25 ,  H03M13/29 ,  H03M13/00

    Abstract: A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to generate a plurality of bit groups each of which is formed of a same number of bits, determine whether a number of the outer-encoded bits satisfies a predetermined number of bits required according to at least one of a code rate and a code length for Low Density Parity Check (LDPC) encoding, pads zero bits to some of the bits in the bit groups if the number of the outer-encoded bits is less than the predetermined number of bits, and maps the outer-encoded bits to remaining bits in the bit groups, based on a predetermined shortening pattern, thereby to constitute LDPC information bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the some of the bits, in which zero bits are padded, are included in some of the bit groups which are not sequentially disposed in the LDPC information bits.

    Transmitter and parity permutation method thereof
    8.
    发明授权
    Transmitter and parity permutation method thereof 有权

    公开(公告)号：US11196448B2

    公开(公告)日：2021-12-07

    申请号：US16390393

    申请日：2019-04-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyung-Joong Kim ,  Se-ho Myung ,  Hong-sil Jeong

    IPC: H03M13/00 ,  H03M13/11 ,  H03M13/25 ,  H03M13/27 ,  H03M13/29 ,  H04L1/00 ,  H04L27/20 ,  H03M13/15

    Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to perform parity permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups including the interleaved parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups, and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups are positioned at predetermined positions, respectively, and a remainder of the bit groups are positioned without an order within the group-wise interleaved bit groups so that the puncturer selects parity bits included in the some of the bit groups positioned at the predetermined positions sequentially and selects parity bits included in the remainder of the bit groups without an order.

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