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    Semiconductor package
    2.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US12300665B2

    公开(公告)日：2025-05-13

    申请号：US17547382

    申请日：2021-12-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jang-woo Lee ,  Un-byoung Kang ,  Ji-hwang Kim ,  Jong-bo Shim ,  Young-kun Jee

    IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

    Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.

    Semiconductor package
    5.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11227855B2

    公开(公告)日：2022-01-18

    申请号：US16407429

    申请日：2019-05-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jang-woo Lee ,  Un-byoung Kang ,  Ji-hwang Kim ,  Jong-bo Shim ,  Young-kun Jee

    IPC: H01L21/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

    Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.

    MEMORY DEVICE FOR EFFICIENTLY DETERMINING WHETHER TO PERFORM RE-TRAINING OPERATION AND MEMORY SYSTEM INCLUDING THE SAME
    6.
    发明申请
    MEMORY DEVICE FOR EFFICIENTLY DETERMINING WHETHER TO PERFORM RE-TRAINING OPERATION AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20190050159A1

    公开(公告)日：2019-02-14

    申请号：US15906266

    申请日：2018-02-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Won-joo Jung ,  Jang-woo Lee ,  Byung-hoon Jeong ,  Jeong-don Ihm

    IPC: G06F3/06

    Abstract: A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.

    Memory device for efficiently determining whether to perform re-training operation and memory system including the same
    8.
    发明授权
    Memory device for efficiently determining whether to perform re-training operation and memory system including the same 有权

    公开(公告)号：US10754563B2

    公开(公告)日：2020-08-25

    申请号：US15906266

    申请日：2018-02-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Won-joo Jung ,  Jang-woo Lee ,  Byung-hoon Jeong ,  Jeong-don Ihm

    IPC: G06F3/06 ,  G06F13/16

    Abstract: A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.

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