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    Method of fabricating semiconductor device
    1.
    发明授权
    Method of fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08962455B2

    公开(公告)日：2015-02-24

    申请号：US13920181

    申请日：2013-06-18

    申请人： SAMSUNG Electronics Co., Ltd.

    发明人： Sang-Hyun Choi ,  Jin-Ho Noh ,  Yoon-Ho Son ,  Dae-Hyuk Chung ,  In-Seak Hwang ,  Tae-Joon Park ,  Tae-Ho Hwang

    IPC分类号： H01L21/36 ,  H01L21/768 ,  H01L21/28 ,  H01L29/78 ,  H01L29/423 ,  H01L27/108

    CPC分类号： H01L21/76841 ,  H01L21/28158 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/7827

    摘要： A method of fabricating a semiconductor device includes forming a first preliminary gate barrier layer and a first preliminary gate electrode recessed to have a first depth from the surface of the substrate within a gate trench, removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant to form a second preliminary gate electrode recessed to have a second depth greater than the first depth, and removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant to form a gate electrode and a gate barrier layer recessed to a third depth greater than the second depth.

    摘要翻译： 制造半导体器件的方法包括：形成第一预栅极势垒层和第一预栅极电极，所述第一预栅极电极凹陷以在栅极沟槽内具有来自衬底的表面的第一深度，通过装置去除第一预栅极的上部 使用第一蚀刻剂形成凹陷以具有大于第一深度的第二深度的第二预选栅电极的第一湿蚀刻工艺，以及去除第一预栅极势垒层的上部和第二预选栅极的上部 电极通过使用第二蚀刻剂的第二湿蚀刻工艺形成栅电极和凹陷到大于第二深度的第三深度的栅极势垒层。