公开(公告)号：US10026492B2

公开(公告)日：2018-07-17

申请号：US15640563

申请日：2017-07-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepanshu Dutta ,  Arash Hazeghi ,  Huai-Yuan Tseng ,  Cynthia Hsu ,  Navneeth Kankani

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/32

Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.

公开(公告)号：US20170309344A1

公开(公告)日：2017-10-26

申请号：US15640563

申请日：2017-07-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepanshu Dutta ,  Arash Hazeghi ,  Huai-Yuan Tseng ,  Cynthia Hsu ,  Navneeth Kankani

IPC: G11C16/34 ,  G11C16/32 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/32

Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.