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    EFFICIENT READ OF NAND WITH READ DISTURB MITIGATION
    1.
    发明申请
    EFFICIENT READ OF NAND WITH READ DISTURB MITIGATION 有权

    公开(公告)号：US20220383961A1

    公开(公告)日：2022-12-01

    申请号：US17329390

    申请日：2021-05-25

    Applicant: SanDisk Technologies LLC

    Inventor： Yu-Chung Lien ,  Tomer Eliash ,  Huai-Yuan Tseng

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08

    Abstract: Technology is disclosed for an efficient read NAND memory cells while mitigating read disturb. In an aspect, a read sequence includes a read spike that removes residual electrons from the NAND channels, followed by reading multiple different groups of memory cells, followed by a channel clean operation. The read spike and channel clean mitigate read disturb. The read spike and channel clean each take a significant amount of time to perform. However, since multiple groups of memory cells are read between the read spike and channel clean this time is essentially spread over the reading of multiple groups, thereby improving the average time to read a single group of memory cells. In one aspect, reading the multiple different groups of memory cells includes reading one or more pages from each of the groups of memory cells. In one aspect, each group is in a different sub-block.

    Countermeasure for reducing peak current during programming by optimizing timing of latch scan operations
    3.
    发明授权
    Countermeasure for reducing peak current during programming by optimizing timing of latch scan operations 有权

    公开(公告)号：US11361835B1

    公开(公告)日：2022-06-14

    申请号：US17188998

    申请日：2021-03-01

    Applicant: SanDisk Technologies LLC

    Inventor： Yu-Chung Lien ,  Fanglin Zhang ,  Huai-Yuan Tseng

    IPC: G11C16/10 ,  G11C16/34 ,  G11C16/08 ,  G11C16/30 ,  G11C16/26

    Abstract: Apparatuses and techniques are described for avoiding current consumption peaks during a program operation for a memory device. The timing of scan operations of latches is adjusted to avoid overlapping with an increase in word line voltages. The scan operations can include a pre-charge select scan, which identifies memory cells subject to a verify test, and a fill operation for latches of memory cells which fail a verify test in a prior program loop. The pre-charge select scan can occur before the increase in the word line voltages, while the fill operation occurs after the increase in word line voltages. In another approach, the start of the increase in the word line voltages is delayed when a state bit scan is expected to take a relatively long time, e.g., when a verify test is passed in a prior program loop.

    Peak and average current reduction for sub block memory operation
    5.
    发明授权
    Peak and average current reduction for sub block memory operation 有权

    公开(公告)号：US11189351B2

    公开(公告)日：2021-11-30

    申请号：US16832293

    申请日：2020-03-27

    Applicant: SanDisk Technologies LLC

    Inventor： Yu-Chung Lien ,  Sarath Puthenthermadam ,  Huai-Yuan Tseng

    IPC: G11C11/34 ,  G11C16/26 ,  G11C16/04 ,  H01L27/11582

    Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells arranged in strings and connected to word lines overlying one another in a stack. The block is divided into first and second sub-blocks programmed as a whole in a sub-block mode and includes a particular group connected to a particular word line. A control circuit determines whether the particular group being read is in the second sub-block when operating in the sub-block mode. The control circuit also determines whether one of the first and second sub-blocks is not programmed based on whether the particular group being read is in the second sub-block. The control circuit applies an adjusted read voltage to the word lines of the one of the first and second sub-blocks while reading the particular group based on whether the one of the first and second sub-blocks is not programmed.

    PEAK AND AVERAGE CURRENT REDUCTION FOR SUB BLOCK MEMORY OPERATION
    7.
    发明申请
    PEAK AND AVERAGE CURRENT REDUCTION FOR SUB BLOCK MEMORY OPERATION 有权

    公开(公告)号：US20210304822A1

    公开(公告)日：2021-09-30

    申请号：US16832293

    申请日：2020-03-27

    Applicant: SanDisk Technologies LLC

    Inventor： Yu-Chung Lien ,  Sarath Puthenthermadam ,  Huai-Yuan Tseng

    IPC: G11C16/26 ,  G11C16/04

    Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells arranged in strings and connected to word lines overlying one another in a stack. The block is divided into first and second sub-blocks programmed as a whole in a sub-block mode and includes a particular group connected to a particular word line. A control circuit determines whether the particular group being read is in the second sub-block when operating in the sub-block mode. The control circuit also determines whether one of the first and second sub-blocks is not programmed based on whether the particular group being read is in the second sub-block. The control circuit applies an adjusted read voltage to the word lines of the one of the first and second sub-blocks while reading the particular group based on whether the one of the first and second sub-blocks is not programmed.

    Interleaved program and verify in non-volatile memory
    9.
    发明授权
    Interleaved program and verify in non-volatile memory 有权

    公开(公告)号：US10885994B2

    公开(公告)日：2021-01-05

    申请号：US16828477

    申请日：2020-03-24

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  H01L27/1157 ,  G11C11/56 ,  H01L27/11524

    Abstract: A circuit includes a program controller configured to perform a program operation with interleaved program-verify loops to program memory cells in a same block. During each program-verify loop, a control gate line voltage supply circuit first supplies a program pulse to a first cell of the block and then, before verifying the first cell, supplies a program pulse to a second cell of the block. After the program pulses are sent, the control gate line supply circuit consecutively supplies verify pulses to the first cell and the second cell such that a delay is introduced between the respective program and verify stages of the first and second cells. Additionally, a constant voltage bias on common control gate lines of the first and second memory cells is applied during the consecutive verify stages. Further, an order of verify pulses may be applied in a reverse order during a verify stage.

    INTERLEAVED PROGRAM AND VERIFY IN NON-VOLATILE MEMORY
    10.
    发明申请
    INTERLEAVED PROGRAM AND VERIFY IN NON-VOLATILE MEMORY 审中-公开

    公开(公告)号：US20200227124A1

    公开(公告)日：2020-07-16

    申请号：US16828477

    申请日：2020-03-24

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

    IPC: G11C16/34 ,  G11C16/10

    Abstract: A circuit includes a program controller configured to perform a program operation with interleaved program-verify loops to program memory cells in a same block. During each program-verify loop, a control gate line voltage supply circuit first supplies a program pulse to a first cell of the block and then, before verifying the first cell, supplies a program pulse to a second cell of the block. After the program pulses are sent, the control gate line supply circuit consecutively supplies verify pulses to the first cell and the second cell such that a delay is introduced between the respective program and verify stages of the first and second cells. Additionally, a constant voltage bias on common control gate lines of the first and second memory cells is applied during the consecutive verify stages. Further, an order of verify pulses may be applied in a reverse order during a verify stage.

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