公开(公告)号：US11676954B2

公开(公告)日：2023-06-13

申请号：US17134997

申请日：2020-12-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani ,  Kwang-ho Kim

IPC: H01L25/065 ,  H01L23/528 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L25/18 ,  H01L23/5286 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers; memory openings extending through the alternating stack, memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film, a source layer contacting the vertical semiconductor channels, a backside isolation dielectric layer contacting a backside surface of the source layer, and a source power supply mesh including a planar portion of a source-side electrically conductive layer that is located on a backside of the backside isolation dielectric layer and electrically connected to the source layer by conductive material portions that extend through the backside isolation dielectric layer.

公开(公告)号：US09748001B2

公开(公告)日：2017-08-29

申请号：US14244726

申请日：2014-04-03

Applicant: SanDisk Technologies LLC

Inventor： Yan Li ,  Kwang-ho Kim ,  Frank Tsai ,  Aldo Bottelli

IPC: G11C11/34 ,  G11C29/00 ,  G11C16/10

CPC classification number: G11C29/00 ,  G11C16/10 ,  G11C29/808

Abstract: Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described. Based on this information, the bad bits can be extracted and re-grouped into bytes by the controller or on the memory to more efficiently use the column redundancy area.