公开(公告)号：US20190267391A1

公开(公告)日：2019-08-29

申请号：US16406283

申请日：2019-05-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Muneyuki IMAI ,  James KAI

IPC: H01L27/11556 ,  H01L21/28 ,  H01L27/11582 ,  H01L29/06 ,  G11C5/02 ,  G11C16/04

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers. The drain-select-level assemblies may be provided by forming drain-select-level openings through a drain-select-level sacrificial material layer, and by forming a combination of a cylindrical electrode portion and a first gate dielectric mayin each first drain-select-level opening while forming a second gate dielectric directly on a sidewall of each second drain-select-level opening in a second subset of the drain-select-level openings. A strip electrode portion is formed by replacing the drain-select-level sacrificial material layer with a conductive material. Structures filling the second subset of the drain-select-level openings may be used as dummy structures at a periphery of an array. The dummy structures are free of gate electrodes and thus prevents a leakage current therethrough.

公开(公告)号：US20210391345A1

公开(公告)日：2021-12-16

申请号：US16900060

申请日：2020-06-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshitaka OTSU ,  Muneyuki IMAI ,  Junpei KANAZAWA

IPC: H01L27/11539 ,  H01L27/11524 ,  H01L27/11519 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method of forming a three-dimensional memory device includes forming a first-tier alternating stack of first insulating layers and first sacrificial material layers, forming first-tier memory openings, first-tier support openings, and first-tier moat trenches through the first alternating stack using a same etching step, forming a first dielectric moat structure in the first moat tier-trenches and first support pillar structures in the first-tier support openings during a same deposition step, forming memory stack structures in the first-tier memory openings, forming backside trenches through the first-tier alternating stack after forming the first dielectric moat structure, replacing portions of the first sacrificial material layers with first electrically conductive layers through the backside trenches, and forming at least one through-memory-level interconnection via structure through the first vertically alternating sequence of first insulating plates and first dielectric material plates surrounded by the first dielectric moat structure.