公开(公告)号：US20200303398A1

公开(公告)日：2020-09-24

申请号：US16361773

申请日：2019-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshitaka OTSU ,  Koichiro NAGATA ,  Junpei KANAZAWA

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and is patterned to form stepped surfaces. Memory stack structures are formed in a memory array region of the alternating stack. Support pillar structures are formed through the vertically alternating sequence within a staircase region. The support pillar structures are formed at lattice sites of a hexagonal lattice structure that includes unoccupied lattice sites. Portions of the continuous sacrificial material layers are replaced with electrically conductive layers. Contact via structures are formed on a respective one of the electrically conductive layers at the unoccupied lattice sites. Geometrical centers of the support pillar structures are arranged at vertices of a polygon having more than four vertices having a respective contact via structure located at a geometric center of the polygon in a plan view.

公开(公告)号：US20210358941A1

公开(公告)日：2021-11-18

申请号：US16876370

申请日：2020-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kengo KAJIWARA ,  Atsushi SHIMODA ,  Tatsuya HINOUE ,  Junpei KANAZAWA ,  Masanori TERAHARA

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L21/768

Abstract: A three-dimensional memory device includes a first-tier structure located over a substrate and including a first alternating stack of first insulating layers and first electrically conductive layers. a second-tier structure located over the first-tier structure and including a second alternating stack of second insulating layers and second electrically conductive layers, memory stack structures vertically extending through the first alternating stack and the second alternating stack, primary support pillar structures, and auxiliary support pillar structures vertically extending through the first alternating stack, underlying the second stepped surfaces, and located below a horizontal plane including a bottommost surface of the second alternating stack.

公开(公告)号：US20210391345A1

公开(公告)日：2021-12-16

申请号：US16900060

申请日：2020-06-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshitaka OTSU ,  Muneyuki IMAI ,  Junpei KANAZAWA

IPC: H01L27/11539 ,  H01L27/11524 ,  H01L27/11519 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method of forming a three-dimensional memory device includes forming a first-tier alternating stack of first insulating layers and first sacrificial material layers, forming first-tier memory openings, first-tier support openings, and first-tier moat trenches through the first alternating stack using a same etching step, forming a first dielectric moat structure in the first moat tier-trenches and first support pillar structures in the first-tier support openings during a same deposition step, forming memory stack structures in the first-tier memory openings, forming backside trenches through the first-tier alternating stack after forming the first dielectric moat structure, replacing portions of the first sacrificial material layers with first electrically conductive layers through the backside trenches, and forming at least one through-memory-level interconnection via structure through the first vertically alternating sequence of first insulating plates and first dielectric material plates surrounded by the first dielectric moat structure.

公开(公告)号：US20210384207A1

公开(公告)日：2021-12-09

申请号：US16893995

申请日：2020-06-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki IWAI ,  Junpei KANAZAWA ,  Hisakazu OTOI ,  Hironori MATSUOKA ,  Raiden MATSUNO

IPC: H01L27/11539 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A three-dimensional memory device can include at least one alternating stack of insulating layers and electrically conductive layers located over a semiconductor material layer, memory stack structures vertically extending through the at least one alternating stack, and a vertical stack of dielectric plates interlaced with laterally extending portions of the insulating layers of the at least one alternating stack. A conductive via structure can vertically extend through each dielectric plate and the insulating layers, and can contact an underlying metal interconnect structure. Additionally or alternatively, support pillar structures can vertically extend through the vertical stack of dielectric plates and into an opening through the semiconductor material layer, and can contact lower-level dielectric material layers embedding the underlying metal interconnect structure to enhance structural support to the three-dimensional memory device during manufacture.

公开(公告)号：US20210210424A1

公开(公告)日：2021-07-08

申请号：US16809861

申请日：2020-03-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshitaka OTSU ,  Masanori TERAHARA ,  Junpei KANAZAWA

IPC: H01L23/522 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11519 ,  H01L23/528 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a perforated dielectric moat structure vertically extending through the alternating stack, and an interconnection via structure laterally surrounded by the perforated dielectric moat structure and vertically extending through each insulating layer within the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the electrically conductive layers. The perforated dielectric moat structure includes a plurality of lateral openings at each level of the insulating layers, and does not include any opening at levels of the electrically conductive layers. An interconnection via structure can be laterally surrounded by the perforated dielectric moat structure, and can vertically extend through each insulating layer within the alternating stack.