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    THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A CAPPED ISOLATION TRENCH FILL STRUCTURE AND METHODS OF MAKING THE SAME
    3.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A CAPPED ISOLATION TRENCH FILL STRUCTURE AND METHODS OF MAKING THE SAME 有权

    公开(公告)号：US20230013984A1

    公开(公告)日：2023-01-19

    申请号：US17376490

    申请日：2021-07-15

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Yoshitaka OTSU

    IPC: H01L23/535 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A semiconductor structure includes semiconductor devices located on a top surface of a substrate semiconductor layer, lower-level metal interconnect structures embedded in lower-level dielectric material layers, source-level material layers, an alternating stack of insulating layers and electrically conductive layers overlying the source-level material layer, memory stack structures, a vertically alternating sequence of insulating plates and dielectric material plates laterally surrounded by the alternating stack, an isolation trench fill structure interposed between the alternating stack and the vertically alternating sequence and including a trench fill material portion and a capping dielectric structure overlying the trench fill material portion, and a first through-memory-level interconnection via structure vertically extending through each plate within the vertically alternating sequence and contacting a top surface of one of the lower-level metal interconnect structures.

    THREE-DIMENSIONAL MEMORY DEVICE WITH DIELECTRIC ISOLATED VIA STRUCTURES AND METHODS OF MAKING THE SAME
    4.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE WITH DIELECTRIC ISOLATED VIA STRUCTURES AND METHODS OF MAKING THE SAME 有权

    公开(公告)号：US20210210503A1

    公开(公告)日：2021-07-08

    申请号：US17106792

    申请日：2020-11-30

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Koichi MATSUNO ,  James KAI ,  Jixin YU ,  Johann ALSMEIER ,  Yoshitaka OTSU

    IPC: H01L27/11575 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11582 ,  H01L21/768

    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises a vertical semiconductor channel and a vertical stack of memory elements, a dielectric moat structure vertically extending through the alternating stack and including an annular dielectric plate portion at each level of the electrically conductive layers that laterally surrounds a respective dielectric material plate, and an interconnection via structure laterally surrounded by the dielectric moat structure and vertically extending through each insulating layer within the alternating stack. Each of the annular dielectric plate portions includes a continuous inner sidewall including a plurality of laterally-convex and vertically-planar inner sidewall segments that are adjoined to each other, and a continuous outer sidewall including a plurality of laterally-convex and vertically-planar outer sidewall segments that are adjoined to each other.

    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING MULTI-TIER MOAT ISOLATION STRUCTURES AND METHODS OF MAKING THE SAME
    8.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING MULTI-TIER MOAT ISOLATION STRUCTURES AND METHODS OF MAKING THE SAME 有权

    公开(公告)号：US20210391345A1

    公开(公告)日：2021-12-16

    申请号：US16900060

    申请日：2020-06-12

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Yoshitaka OTSU ,  Muneyuki IMAI ,  Junpei KANAZAWA

    IPC: H01L27/11539 ,  H01L27/11524 ,  H01L27/11519 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A method of forming a three-dimensional memory device includes forming a first-tier alternating stack of first insulating layers and first sacrificial material layers, forming first-tier memory openings, first-tier support openings, and first-tier moat trenches through the first alternating stack using a same etching step, forming a first dielectric moat structure in the first moat tier-trenches and first support pillar structures in the first-tier support openings during a same deposition step, forming memory stack structures in the first-tier memory openings, forming backside trenches through the first-tier alternating stack after forming the first dielectric moat structure, replacing portions of the first sacrificial material layers with first electrically conductive layers through the backside trenches, and forming at least one through-memory-level interconnection via structure through the first vertically alternating sequence of first insulating plates and first dielectric material plates surrounded by the first dielectric moat structure.

    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING THROUGH-MEMORY-LEVEL VIA STRUCTURES AND METHODS OF MAKING THE SAME
    9.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING THROUGH-MEMORY-LEVEL VIA STRUCTURES AND METHODS OF MAKING THE SAME 有权

    公开(公告)号：US20210384206A1

    公开(公告)日：2021-12-09

    申请号：US16893933

    申请日：2020-06-05

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Takaaki IWAI ,  Yoshitaka OTSU ,  Hirofumi TOKITA

    IPC: H01L27/11539 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A three-dimensional memory device can include at least one alternating stack of insulating layers and electrically conductive layers located over a semiconductor material layer, memory stack structures vertically extending through the at least one alternating stack, and a vertical stack of dielectric plates interlaced with laterally extending portions of the insulating layers of the at least one alternating stack. A conductive via structure can vertically extend through each dielectric plate and the insulating layers, and can contact an underlying metal interconnect structure. Additionally or alternatively, support pillar structures can vertically extend through the vertical stack of dielectric plates and into an opening through the semiconductor material layer, and can contact lower-level dielectric material layers embedding the underlying metal interconnect structure to enhance structural support to the three-dimensional memory device during manufacture.

    THREE-DIMENSIONAL MEMORY DEVICE WITH VIA STRUCTURES SURROUNDED BY PERFORATED DIELECTRIC MOAT STRUCTURE AND METHODS OF MAKING THE SAME
    10.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE WITH VIA STRUCTURES SURROUNDED BY PERFORATED DIELECTRIC MOAT STRUCTURE AND METHODS OF MAKING THE SAME 有权

    公开(公告)号：US20210210504A1

    公开(公告)日：2021-07-08

    申请号：US16735854

    申请日：2020-01-07

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Yoshitaka OTSU ,  Kenichi OKABE ,  Takashi ARAI

    IPC: H01L27/11582 ,  H01L23/522 ,  H01L21/768

    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a perforated dielectric moat structure vertically extending through the alternating stack, and an interconnection via structure laterally surrounded by the perforated dielectric moat structure and vertically extending through each insulating layer within the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the electrically conductive layers. The perforated dielectric moat structure includes a plurality of lateral openings at each level of the insulating layers, and does not include any opening at levels of the electrically conductive layers.

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