公开(公告)号：US20210384207A1

公开(公告)日：2021-12-09

申请号：US16893995

申请日：2020-06-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki IWAI ,  Junpei KANAZAWA ,  Hisakazu OTOI ,  Hironori MATSUOKA ,  Raiden MATSUNO

IPC: H01L27/11539 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A three-dimensional memory device can include at least one alternating stack of insulating layers and electrically conductive layers located over a semiconductor material layer, memory stack structures vertically extending through the at least one alternating stack, and a vertical stack of dielectric plates interlaced with laterally extending portions of the insulating layers of the at least one alternating stack. A conductive via structure can vertically extend through each dielectric plate and the insulating layers, and can contact an underlying metal interconnect structure. Additionally or alternatively, support pillar structures can vertically extend through the vertical stack of dielectric plates and into an opening through the semiconductor material layer, and can contact lower-level dielectric material layers embedding the underlying metal interconnect structure to enhance structural support to the three-dimensional memory device during manufacture.

公开(公告)号：US20210050360A1

公开(公告)日：2021-02-18

申请号：US16539124

申请日：2019-08-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Johann ALSMEIER ,  Murshed CHOWDHURY ,  Raiden MATSUNO

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C5/06

Abstract: A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, gate electrodes vertically extending through each of the source layers and the drain layers of the alternating stack, memory films laterally surrounding a respective one of the gate electrodes, and semiconductor channels laterally surrounding a respective one of the memory films and connected to a respective vertically neighboring pair of a source layer and a drain layer. An array of memory openings can vertically extend through the alternating stack, and each of the gate electrodes can be located within a respective one of the memory openings.