公开(公告)号：US20230223356A1

公开(公告)日：2023-07-13

申请号：US17574182

申请日：2022-01-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shin SAKIYAMA ,  Genta MIZUNO ,  Kenzo IIZUKA ,  Takayuki YOKOYAMA ,  Toshiyuki SEGA

IPC: H01L23/00 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L24/08 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L25/0657 ,  H01L27/11556 ,  H01L27/11582 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/3511 ,  H01L2924/14511

Abstract: A memory die includes dielectric isolation rails embedded within a substrate semiconductor layer, laterally spaced apart along a first horizontal direction, and each laterally extending along a second horizontal direction that is perpendicular to the first horizontal direction, and alternating stacks of insulating layers and electrically conductive layers located over the substrate semiconductor layer. The alternating stacks are laterally spaced apart along the second horizontal direction by line trenches that laterally extend along the first horizontal direction. Arrays of memory stack structures are provided such that each array of memory stack structures among the arrays of memory stack structures vertically extends through a respective alternating stack. Each of the memory stack structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel.