公开(公告)号：US20230057885A1

公开(公告)日：2023-02-23

申请号：US17406463

申请日：2021-08-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ryousuke ITOU ,  Akihisa SAI ,  Kenzo IIZUKA

IPC: H01L23/522 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/311 ,  H01L21/768

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and memory opening fill structures including vertical stacks of memory elements are formed through the vertically alternating sequence. Backside trenches are formed to divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers. A set of one or more bridge structures including a doped semiconductor material is formed within each of the backside trenches. The sacrificial material layers are replaced with electrically conductive layers while the sets of at least one bridge structure are present within the backside trenches.

公开(公告)号：US20230223356A1

公开(公告)日：2023-07-13

申请号：US17574182

申请日：2022-01-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shin SAKIYAMA ,  Genta MIZUNO ,  Kenzo IIZUKA ,  Takayuki YOKOYAMA ,  Toshiyuki SEGA

IPC: H01L23/00 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L24/08 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L25/0657 ,  H01L27/11556 ,  H01L27/11582 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/3511 ,  H01L2924/14511

Abstract: A memory die includes dielectric isolation rails embedded within a substrate semiconductor layer, laterally spaced apart along a first horizontal direction, and each laterally extending along a second horizontal direction that is perpendicular to the first horizontal direction, and alternating stacks of insulating layers and electrically conductive layers located over the substrate semiconductor layer. The alternating stacks are laterally spaced apart along the second horizontal direction by line trenches that laterally extend along the first horizontal direction. Arrays of memory stack structures are provided such that each array of memory stack structures among the arrays of memory stack structures vertically extends through a respective alternating stack. Each of the memory stack structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel.

公开(公告)号：US20230055230A1

公开(公告)日：2023-02-23

申请号：US17530861

申请日：2021-11-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ryousuke ITOU ,  Akihisa SAI ,  Kenzo IIZUKA

IPC: H01L23/522 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/3213 ,  H01L21/768

Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and memory opening fill structures including vertical stacks of memory elements are formed through the vertically alternating sequence. Backside trenches are formed to divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers. Bridge structures are formed within each of the backside trenches. The sacrificial material layers are replaced with electrically conductive layers while the bridge structure are present within the backside trenches.

公开(公告)号：US20220254733A1

公开(公告)日：2022-08-11

申请号：US17174064

申请日：2021-02-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Genta MIZUNO ,  Kenzo IIZUKA ,  Satoshi SHIMIZU ,  Keisuke IZUMI ,  Tatsuya HINOUE ,  Yujin TERASAWA ,  Seiji SHIMABUKURO ,  Ryousuke ITOU ,  Yanli ZHANG ,  Johann ALSMEIER ,  Yusuke YOSHIDA

IPC: H01L23/00 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region.