公开(公告)号：US20180130812A1

公开(公告)日：2018-05-10

申请号：US15347101

申请日：2016-11-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Takeshi KAWAMURA ,  Yoko FURIHATA ,  Kota FUNAYAMA

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings are formed through the first tier structure. A dielectric material portion providing electrical isolation from the substrate is formed in each first memory openings. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed the first tier structure. Second support openings and second memory openings are formed through the second tier structure above the first support openings and the first memory openings. Memory stack structures are formed in inter-tier openings formed by adjoining the first and second memory openings. The dielectric material portions provide electrical isolation between the substrate and the vertical semiconductor layers formed within support pillar structures to prevent or reduce electrical shorts to the substrate through the support pillar structures.