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1.发明公开公开(公告)号：US20240305305A1
公开(公告)日：2024-09-12
申请号：US18573158
申请日：2022-03-28
Applicant: SANECHIPS TECHNOLOGY CO., LTD.
Inventor： Wen CAO , Rui PANG , Yanyan ZHAO
CPC classification number: H03L7/0992 , H03L7/083
Abstract: The present application provides a clock switching method, a clock switching apparatus, an electronic device, and a readable storage medium, the clock switching method includes: in a case where a first reference clock is determined to be in a locked state, determining an average control word according to a preset duration and an obtained real frequency tuning word; in a case where the first reference clock is determined to be in an invalid state, determining a compensation phase difference by using the average control word as a frequency control word of a digital phase locked loop; performing a phase compensation on a second reference clock according to the compensation phase difference to obtain an updated second reference clock; and switching the first reference clock to the updated second reference clock.
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公开(公告)号：US20240405797A1
公开(公告)日：2024-12-05
申请号：US18697029
申请日：2022-03-02
Applicant: SANECHIPS TECHNOLOGY CO., LTD.
Inventor： Yanyan ZHAO , Wen CAO , Minna XIE , Huan JING
IPC: H04B1/525
Abstract: The present disclosure provides a full-duplex digital self-interference clear method, including: before a signal is transmitted with a peer device in a full-duplex mode, performing a calculation by a self-adaptive algorithm to obtain a pre-distortion processing coefficient; under the condition that the signal is transmitted with the peer device in the full-duplex mode, performing pre-distortion processing on a first signal sent by the transmit link to the peer device according to the pre-distortion processing coefficient to obtain a second reconstructed interference signal; and performing self-interference clear according to the second reconstructed interference signal and a second interference signal of the receive link, with the second interference signal being a signal obtained through superimposition of an interference signal generated by the first signal in the receive link and a second signal received by the receive link from the peer device. The present disclosure further provides a full-duplex digital self-interference clear apparatus.
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公开(公告)号：US20240380404A1
公开(公告)日：2024-11-14
申请号：US18696385
申请日：2022-09-19
Applicant: SANECHIPS TECHNOLOGY CO., LTD.
Abstract: The present disclosure provides a linearity calibration method for digital time converter, including: acquiring a phase prediction parameter and a locked phase error, and calculating a control word of a digital time converter according to the phase prediction parameter, the locked phase error, a pre-configured nonlinear predistortion function, and a pre-configured calibration order n, with the control word being configured to enable the digital time converter to adjust a delay of a reference clock, so as to keep the reference clock and a feedback clock which are input to a time digital converter in a tracked state. The present disclosure further provides a linearity calibration apparatus for digital time converter and a digital phase lock loop.
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