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公开(公告)号：US20250007927A1
公开(公告)日：2025-01-02
申请号：US18708249
申请日：2022-03-21
Applicant: SANECHIPS TECHNOLOGY CO., LTD.
Inventor： Zhenfeng ZHANG , Hao SUN , Zhengxiang LI , Kun WANG , Sai WANG
IPC: H04L9/40
Abstract: Embodiments of the present disclosure relate to the field of communication transmission, and in particular, to a network anti-replay method and apparatus, an electronic device, and a storage medium. The network anti-replay method includes: according to a current packet number of a currently received data packet, determining a section to which the current packet number belongs in a replay window, with the replay window being divided into a plurality of sections, and each of the plurality of sections being configured to record packet numbers of L received data packets which belong to the section; and L being smaller than T, and T being a total number of packet numbers belonging to the section; and in a case where the current packet number is not coincident with packet numbers recorded in the determined section to which the current packet number belongs and the current packet number is not coincident with packet numbers of recently received N historical data packets, performing integrity authentication on the currently received data packet, with N being a natural number greater than 1.
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公开(公告)号：US20250007525A1
公开(公告)日：2025-01-02
申请号：US18709161
申请日：2022-03-19
Applicant: SANECHIPS TECHNOLOGY CO.,LTD
Inventor： Licheng ZHU
Abstract: A clock synchronization system and method are provided. The clock synchronization system includes: a pulse generation module, configured to receive an input first signal, perform sampling processing of the first signal to obtain a second signal, and generate a pulse signal according to the second signal; a voltage-controlled oscillator, configured to output a first output clock; the output frequency divider module, configured to perform frequency division on the first output clock, and synchronize, according to the pulse signal, the first output clock which has been subjected to the frequency division, so as to obtain a second output clock; and the synchronous output module, configured to receive the first output clock, the second output clock, the first signal, and the pulse signal, and perform synchronization processing on the first signal according to the first output clock, the second output clock and the pulse signal, so as to obtain a third signal.
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公开(公告)号：US20250007481A1
公开(公告)日：2025-01-02
申请号：US18709090
申请日：2022-03-21
Applicant: SANECHIPS TECHNOLOGY CO., LTD.
Inventor： Siyu LIN
Abstract: Provided in the present disclosure is a variable gain amplifier, including: a voltage signal input end; a high level generation module including two high level signal output ends, and configured to convert a voltage signal input from the voltage signal input end into a first high level signal and a second high level signal; a switch signal conversion module including a high level signal input end, N digital signal input ends and N switch signal output ends, and configured to output, through corresponding switch signal output ends and under the control of signals input from the digital signal input ends, gain control signals associated with a signal output from the first high level signal output end; and an amplification module including an amplification unit and N stages of gain control units, where N is a positive integer not less than 1. Further provided is a transmitting apparatus.
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公开(公告)号：US20240426883A1
公开(公告)日：2024-12-26
申请号：US18687909
申请日：2022-03-19
Applicant: SANECHIPS TECHNOLOGY CO., LTD.
Inventor： Niuyi SUN , Dan YANG , Na MEI , Tuobei SUN
Abstract: A circuit for acquiring a resistance value of a resistor includes: a working voltage node resistor Rb, a common ground voltage node resistor Rc, a reference node resistor Ra, a first interconnect parasitic resistor Rwire1, a second interconnect parasitic resistor Rwire2, an encapsulation network resistor Rnet, a first diode Dio_VDD, a Dio_Vss, and a Dio_die, wherein the working voltage node resistor Rb is respectively connected to one end of the Rwire1 and one end of the encapsulation network resistor Rnet. The other end of the Rwire1 is connected to a negative electrode of the Dio_VDD, and a positive electrode of the Dio_VDD is respectively connected to the Ra and a negative electrode of the Dio_Vss. A positive electrode of the Dio_VSS is respectively connected to the Rc and a negative electrode of the Dio_die via the Rwire2. A positive electrode of the Dio_die is connected to the other end of the Rnet.
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公开(公告)号：US20240411555A1
公开(公告)日：2024-12-12
申请号：US18717053
申请日：2022-12-05
Applicant: SANECHIPS TECHNOLOGY CO., LTD.
Inventor： Hong LEI , Degen ZHEN , Tongqing WU , Dehui KONG , Ke XU
IPC: G06F9/30
Abstract: There are provided a vector operation method, a vector operator, an electronic device, and a computer-readable storage medium. The vector operation method includes: splitting a target vector operation to be performed to determine a plurality of basic operations in a predetermined execution order; sequentially generating, according to the predetermined execution order, a plurality of basic operation instructions corresponding to the plurality of basic operations; and sequentially executing, according to the predetermined execution order, the plurality of basic operation instructions on initial data to be subjected to the target vector operation, so as to implement the target vector operation on the initial data, wherein in two adjacent basic operations, to-be-calculated data for a latter basic operation is an operation result of a former basic operation.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20240394836A1
公开(公告)日：2024-11-28
申请号：US18694974
申请日：2022-03-16
Applicant: SANECHIPS TECHNOLOGY CO., LTD.
Inventor： Cong REN , Hengqi LIU , Ke XU , Dehui KONG , Jisong AI , Xin LIU , Jing YOU
IPC: G06T5/20
Abstract: The present disclosure provides a method for training an image enhancement model, the image enhancement model includes an enhancement module including convolution branches corresponding to brightness intervals; and the method includes: inputting a sample image to the image enhancement model, and acquire a result image output by the image enhancement model; calculating losses including an image loss of the result image relative to a Ground Truth image, and a first constraint loss of brightness histogram constraint of each of the convolution branches of an image output from each of the convolution branches relative to the Ground Truth image; adjusting the enhancement module according to the losses; and in a case where a training end condition is not met, returning to the operation of inputting the sample image to the image enhancement model. The present disclosure further provides an image enhancement method and a computer-readable medium.
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公开(公告)号：US20240388258A1
公开(公告)日：2024-11-21
申请号：US18693844
申请日：2022-03-02
Applicant: SANECHIPS TECHNOLOGY CO., LTD.
Inventor： Xiaoming SI , Nan LIU , Jie HU
Abstract: Provided are a power amplification apparatus and a transmitter. The power amplification apparatus includes power amplification modules each including a voltage output unit and a power amplification unit; the voltage output unit outputs a first voltage signal (VIN_A) and a second voltage signal (VIN_B). The power amplification unit includes a selector (MUX), a radio frequency processing circuit, and a first switch transistor (M1), the radio frequency processing circuit processes a baseband signal to output a first radio frequency signal to a source of the first switch transistor (M1), and the selector (MUX) is configured to correspondingly strobe the first voltage signal (VIN_A) or the second voltage signal (VIN_B) according to an operating state of the first switch transistor (M1).
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公开(公告)号：US12143251B2
公开(公告)日：2024-11-12
申请号：US18012289
申请日：2021-05-25
Applicant: SANECHIPS TECHNOLOGY CO., LTD
Inventor： Mingjie Kong , Xiongjie Shen
Abstract: Provided are a multilevel output drive circuit and method. The circuit includes: a signal selection module, configured to selectively output a signal to be transmitted of a corresponding channel according to an external input signal; a weight generation module, configured to generate weight data according to a weight of an output eye diagram, wherein the weight of the output eye diagram and the weight data are multi-bit binary data; a coefficient transfer module, configured to perform weight control on the signal to be transmitted according to the weight data and generate data containing weight information; and a weight adjustment and data outputting module, configured to perform weight adjustment and pulse amplitude modulation calculation according to weight adjustment control data, the signal to be transmitted and the data containing weight information, and generate PAM4 data.
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9.发明公开公开(公告)号：US20240333315A1
公开(公告)日：2024-10-03
申请号：US18579534
申请日：2022-03-14
Applicant: SANECHIPS TECHNOLOGY CO., LTD.
Inventor： Jialong DING
Abstract: The present application provides a pattern information acquisition method and apparatus, an electronic device, and a readable storage medium. The method includes: sorting, according to reliability weight information of polar codes, a sequence to be processed to obtain a weight-based sequence; performing sequence search on the weight-based sequence to obtain a search result sequence, where the sequence search is used for acquiring a sequence corresponding to data having a reliability weight within a preset reliability threshold range; and mapping the search result sequence to the sequence to be processed to obtain pattern information that indicates position information of data of the search result sequence in the sequence to be processed.
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10.发明公开公开(公告)号：US20240305305A1
公开(公告)日：2024-09-12
申请号：US18573158
申请日：2022-03-28
Applicant: SANECHIPS TECHNOLOGY CO., LTD.
Inventor： Wen CAO , Rui PANG , Yanyan ZHAO
CPC classification number: H03L7/0992 , H03L7/083
Abstract: The present application provides a clock switching method, a clock switching apparatus, an electronic device, and a readable storage medium, the clock switching method includes: in a case where a first reference clock is determined to be in a locked state, determining an average control word according to a preset duration and an obtained real frequency tuning word; in a case where the first reference clock is determined to be in an invalid state, determining a compensation phase difference by using the average control word as a frequency control word of a digital phase locked loop; performing a phase compensation on a second reference clock according to the compensation phase difference to obtain an updated second reference clock; and switching the first reference clock to the updated second reference clock.
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