公开(公告)号：US20240356551A1

公开(公告)日：2024-10-24

申请号：US18575154

申请日：2022-03-02

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Wentao ZHU ,  Yunfeng CHANG ,  Hao LUO ,  Yuhu CHEN ,  Haipeng ZHU ,  Yumei DIAO

IPC: H03K19/0185 ,  H03L7/08 ,  H03M1/00

CPC classification number: H03K19/018507 ,  H03L7/08 ,  H03M1/00

Abstract: Provided in the present disclosure is a clock receiving circuit. The clock receiving circuit comprises a common-mode voltage adjustment module, an amplitude amplification module and a level conversion module. The common-mode voltage adjustment module comprises an n-type signal conversion unit, a high-level n-type signal output end, a low-level n-type signal output end, a p-type signal conversion unit, a high-level p-type signal output end and a low-level p-type signal output end. The amplitude amplification module comprises a p-type current source transistor, an n-type current source transistor, a p-type transistor differential pair, an n-type transistor differential pair and a bias control unit. The level conversion module is used for converting, into a CMOS level signal, a CML level signal which is output by the amplitude amplification circuit. Further provided in the present disclosure is an electronic device comprising the clock receiving circuit.