公开(公告)号：US10804626B2

公开(公告)日：2020-10-13

申请号：US16736277

申请日：2020-01-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jie Chang ,  Huibin Chen ,  Tiburcio Maldo ,  Keunhyuk Lee

IPC: H01R12/58 ,  H01L23/495 ,  H01L23/498 ,  H01R13/03 ,  H05K3/30

Abstract: Implementations of semiconductor packages may include: one or more die electrically coupled to a lead frame. The lead frame may be included within a housing. The semiconductor package may also include a set of signal leads extending from the housing, a set of power leads extending from the housing, and a plurality of press fit pins each fixedly coupled to the set of signal leads and the set of power leads. The set of signal leads and the set of power leads may be configured to couple with a substrate.

公开(公告)号：US10566713B2

公开(公告)日：2020-02-18

申请号：US15865498

申请日：2018-01-09

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jie Chang ,  Huibin Chen ,  Tiburcio Maldo ,  Keunhyuk Lee

IPC: H01R12/58 ,  H01L23/495 ,  H01L23/498 ,  H01R13/03 ,  H05K3/30

Abstract: Implementations of semiconductor packages may include: one or more die electrically coupled to a lead frame. The lead frame may be included within a housing. The semiconductor package may also include a set of signal leads extending from the housing, a set of power leads extending from the housing, and a plurality of press fit pins each fixedly coupled to the set of signal leads and the set of power leads. The set of signal leads and the set of power leads may be configured to couple with a substrate.

公开(公告)号：US10553517B2

公开(公告)日：2020-02-04

申请号：US15874355

申请日：2018-01-18

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jie Chang ,  HuiBin Chen ,  Keunhyuk Lee ,  Jerome Teysseyre

IPC: H01L23/473 ,  H01L23/367 ,  H01L23/31 ,  H01L23/373 ,  H01L23/00 ,  H01L25/18 ,  H01L25/11 ,  H01L25/00 ,  H02M7/5387

Abstract: In one general aspect, a package can include a first submodule including a first semiconductor die coupled to a first substrate and a first spacer, and disposed between the first spacer and the first substrate. The first submodule includes a second spacer disposed lateral to the first semiconductor die. The package includes a second submodule including a second semiconductor die coupled to a second substrate and a third spacer, and disposed between the third spacer and the second substrate. The second submodule includes a fourth spacer disposed lateral to the second semiconductor die. The package includes an inter-module layer disposed between the first submodule and the second submodule. The first spacer of the first submodule is electrically coupled to the fourth spacer of the second-submodule via the inter-module layer. The second spacer of the first submodule is electrically coupled to the third spacer of the second-submodule via the inter-module layer.

公开(公告)号：US12119576B2

公开(公告)日：2024-10-15

申请号：US17064663

申请日：2020-10-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jie Chang ,  Huibin Chen ,  Tiburcio Maldo ,  Keunhyuk Lee

IPC: H01R12/58 ,  H01L23/495 ,  H01L23/498 ,  H01R13/03 ,  H05K3/30

CPC classification number: H01R12/585 ,  H01L23/49517 ,  H01L23/49541 ,  H01L23/49555 ,  H01L23/49579 ,  H01L23/49811 ,  H01R13/03 ,  H05K3/308 ,  H05K2201/1059

Abstract: Implementations of semiconductor packages may include: one or more die electrically coupled to a lead frame. The lead frame may be included within a housing. The semiconductor package may also include a set of signal leads extending from the housing, a set of power leads extending from the housing, and a plurality of press fit pins each fixedly coupled to the set of signal leads and the set of power leads. The set of signal leads and the set of power leads may be configured to couple with a substrate.

公开(公告)号：US11127651B2

公开(公告)日：2021-09-21

申请号：US16732192

申请日：2019-12-31

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jie Chang ,  HuiBin Chen ,  Keunhyuk Lee ,  Jerome Tysseyre

IPC: H01L23/473 ,  H01L23/367 ,  H01L23/31 ,  H01L23/373 ,  H01L23/00 ,  H01L25/18 ,  H01L25/11 ,  H01L25/00 ,  H01L23/433 ,  H01L23/495 ,  H02M7/5387 ,  H02M7/00

Abstract: In one general aspect, a package can include a first submodule including a first semiconductor die coupled to a first substrate and a first spacer, and disposed between the first spacer and the first substrate. The first submodule includes a second spacer disposed lateral to the first semiconductor die. The package includes a second submodule including a second semiconductor die coupled to a second substrate and a third spacer, and disposed between the third spacer and the second substrate. The second submodule includes a fourth spacer disposed lateral to the second semiconductor die. The package includes an inter-module layer disposed between the first submodule and the second submodule. The first spacer of the first submodule is electrically coupled to the fourth spacer of the second-submodule via the inter-module layer. The second spacer of the first submodule is electrically coupled to the third spacer of the second-submodule via the inter-module layer.

公开(公告)号：US11776871B2

公开(公告)日：2023-10-03

申请号：US17247525

申请日：2020-12-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Leo Gu ,  Sixin Ji ,  Jie Chang ,  Keunhyuk Lee ,  Yong Liu

IPC: H01L23/373 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/3735 ,  H01L21/4871 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32237 ,  H01L2224/83815

Abstract: In one general aspect, an apparatus can include a semiconductor component, a substrate including a recess, and a conductive-bonding component. The conductive-bonding component is disposed between the semiconductor component and the substrate. The conductive-bonding component has a first thickness between a bottom of the recess and a bottom surface of the semiconductor component greater than a second thickness between the top of the substrate and the bottom surface of the semiconductor component.