公开(公告)号：US20240204111A1

公开(公告)日：2024-06-20

申请号：US18066738

申请日：2022-12-15

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Alexander Viktorovich BOLOTNIKOV ,  Jimmy Robert Hannes FRANCHI ,  Krister GUMAELIUS

IPC分类号： H01L29/808 ,  H01L21/04 ,  H01L29/16 ,  H01L29/66

CPC分类号： H01L29/8083 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068

摘要： A JFET transistor device having a reduced pitch may be manufactured using self-alignment techniques, while avoiding misalignments that may lead to decreased breakdown voltage and/or increased RDSon. Consequently, described devices provide, for a given active area and gate voltage, additional current channels, increased current, and reduced RDSon, as compared to conventional devices, while retaining high BVgs values.

公开(公告)号：US20240153850A1

公开(公告)日：2024-05-09

申请号：US18053177

申请日：2022-11-07

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Jimmy Robert Hannes FRANCHI ,  Krister GUMAELIUS ,  Jaein AN

IPC分类号： H01L23/482 ,  H01L21/82 ,  H01L23/532 ,  H01L27/082 ,  H01L27/088 ,  H01L29/16

CPC分类号： H01L23/4824 ,  H01L21/8213 ,  H01L23/53257 ,  H01L27/0823 ,  H01L27/088 ,  H01L29/1608

摘要： A semiconductor device may include a plurality of transistors, with a first array of low-resistance material formed in a first dielectric layer, with a gate subset of the first array formed on a plurality of gate electrodes of the transistors, and a source subset of the first array formed on a plurality of source regions of the transistors. A second array of low-resistance material may be formed in a second dielectric layer, with a gate subset of the second array formed on the gate subset of the first array and thereby electrically connected to the plurality of gate electrodes, and a source subset of the second array formed on the source subset of the first array and thereby electrically connected to the plurality of source regions.