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公开(公告)号:US20240153850A1
公开(公告)日:2024-05-09
申请号:US18053177
申请日:2022-11-07
IPC分类号: H01L23/482 , H01L21/82 , H01L23/532 , H01L27/082 , H01L27/088 , H01L29/16
CPC分类号: H01L23/4824 , H01L21/8213 , H01L23/53257 , H01L27/0823 , H01L27/088 , H01L29/1608
摘要: A semiconductor device may include a plurality of transistors, with a first array of low-resistance material formed in a first dielectric layer, with a gate subset of the first array formed on a plurality of gate electrodes of the transistors, and a source subset of the first array formed on a plurality of source regions of the transistors. A second array of low-resistance material may be formed in a second dielectric layer, with a gate subset of the second array formed on the gate subset of the first array and thereby electrically connected to the plurality of gate electrodes, and a source subset of the second array formed on the source subset of the first array and thereby electrically connected to the plurality of source regions.
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公开(公告)号:US20190088740A1
公开(公告)日:2019-03-21
申请号:US16191070
申请日:2018-11-14
发明人: Hideaki Tsuchiko
IPC分类号: H01L29/06 , H01L21/8222 , H01L27/06 , H01L21/8234 , H01L21/761 , H01L27/082 , H01L27/088 , H01L21/8228 , H01L29/66 , H01L29/732 , H01L29/78 , H01L29/10 , H01L29/735 , H01L29/861 , H01L29/423
CPC分类号: H01L29/0649 , H01L21/761 , H01L21/8222 , H01L21/8228 , H01L21/823481 , H01L21/823493 , H01L27/0623 , H01L27/0629 , H01L27/0635 , H01L27/0821 , H01L27/0823 , H01L27/088 , H01L29/063 , H01L29/10 , H01L29/1079 , H01L29/1083 , H01L29/42368 , H01L29/66272 , H01L29/732 , H01L29/735 , H01L29/7816 , H01L29/7835 , H01L29/8611
摘要: The present invention is directed to a semiconductor chip comprising a high voltage device and a low voltage device disposed thereon. The chip may be formed in several different configurations. For example, the semiconductor chip may include a NPN bipolar transistor, PNP bipolar transistor, a diode, an N channel DMOS transistor and the like. the first doped well being configured as a base of the DMOS transistor, a P channel DMOS transistor and the like. These and other embodiments are described in further detail below.
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公开(公告)号:US20180145160A1
公开(公告)日:2018-05-24
申请号:US15360295
申请日:2016-11-23
申请人: GLOBALFOUNDRIES INC.
IPC分类号: H01L29/737 , H01L27/082 , H01L29/16 , H01L29/161 , H01L29/167 , H01L29/04 , H01L29/06 , H01L21/8222 , H01L29/66 , H01L21/02 , H01L21/268 , H01L21/324 , H03F3/21
CPC分类号: H01L29/7375 , H01L21/02532 , H01L21/02592 , H01L21/02675 , H01L21/268 , H01L21/324 , H01L21/8222 , H01L27/0823 , H01L27/0825 , H01L29/04 , H01L29/0649 , H01L29/0653 , H01L29/16 , H01L29/161 , H01L29/167 , H01L29/66242 , H01L29/7371 , H03F3/21 , H03F2200/294
摘要: The present disclosure generally relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor device integration schemes on a same wafer and methods of manufacture. The structure includes: a power amplifier (PA) device comprising a base, a collector and an emitter on a wafer; and a low-noise amplifier (LNA) device comprising a base, a collector and an emitter on the wafer, with the emitter having a same crystalline structure as the base.
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公开(公告)号:US09793346B2
公开(公告)日:2017-10-17
申请号:US15407731
申请日:2017-01-17
发明人: Hamza Yilmaz , Madhur Bobde
IPC分类号: H01L29/66 , H01L29/06 , H01L29/40 , H01L29/739 , H01L29/78 , H01L27/088 , H01L27/082
CPC分类号: H01L29/0623 , H01L27/0823 , H01L27/088 , H01L29/0619 , H01L29/0638 , H01L29/404 , H01L29/407 , H01L29/7393 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L29/7823
摘要: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region.
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公开(公告)号:US20170243939A1
公开(公告)日:2017-08-24
申请号:US15588859
申请日:2017-05-08
发明人: Isao OBU , Shigeru YOSHIDA
IPC分类号: H01L29/10 , H01L29/205 , H03F1/56 , H01L27/082 , H03F3/21 , H01L29/737 , H01L29/73
CPC分类号: H01L29/1004 , H01L27/0823 , H01L27/1022 , H01L29/0692 , H01L29/0817 , H01L29/205 , H01L29/41708 , H01L29/66234 , H01L29/7304 , H01L29/732 , H01L29/7371 , H03F1/56 , H03F3/21 , H03F2200/222 , H03F2200/318 , H03F2200/387 , H03F2200/411
摘要: A high-performance HBT that is unlikely to decrease the process controllability and to increase the manufacturing cost is implemented. A heterojunction bipolar transistor includes an emitter layer, a base layer, and a collector layer on a GaAs substrate. The emitter layer is formed of InGaP. The base layer is formed of GaAsPBi having a composition that substantially lattice-matches GaAs.
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公开(公告)号:US09659901B2
公开(公告)日:2017-05-23
申请号:US14710184
申请日:2015-05-12
申请人: ROHM CO., LTD.
发明人: Akihiro Hikasa
IPC分类号: H01L29/04 , H01L23/00 , H01L25/16 , H01L29/861 , H01L29/739 , H01L29/16 , H01L29/417 , H01L27/082 , H01L23/495 , H01L23/482 , H01L23/40
CPC分类号: H01L29/66333 , H01L23/4006 , H01L23/4824 , H01L23/49562 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/16 , H01L27/082 , H01L27/0823 , H01L27/0825 , H01L29/04 , H01L29/0619 , H01L29/0696 , H01L29/16 , H01L29/407 , H01L29/417 , H01L29/41708 , H01L29/42376 , H01L29/739 , H01L29/7397 , H01L29/861 , H01L2224/05552 , H01L2224/05554 , H01L2224/0603 , H01L2224/291 , H01L2224/32245 , H01L2224/45124 , H01L2224/48091 , H01L2224/48101 , H01L2224/48137 , H01L2224/48247 , H01L2224/48472 , H01L2224/4903 , H01L2224/49111 , H01L2224/49113 , H01L2224/49175 , H01L2224/73265 , H01L2924/1203 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/1815 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/014
摘要: A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.
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公开(公告)号:US09564429B2
公开(公告)日:2017-02-07
申请号:US14751101
申请日:2015-06-25
发明人: Jin Cai , Tak H. Ning , Jeng-Bang Yau , Sufi Zafar
IPC分类号: H01L29/66 , H01L27/082 , H01L29/735 , H01L29/10 , H01L29/161 , H01L29/737 , H01L29/06 , H01L23/31 , H01L21/8222 , G01T1/02
CPC分类号: H01L29/6625 , G01J5/20 , H01L21/8222 , H01L23/3171 , H01L27/0823 , H01L29/0653 , H01L29/1008 , H01L29/161 , H01L29/66242 , H01L29/735 , H01L29/737 , H01L31/1105 , H01L31/115
摘要: An integrated sensor for detecting the presence of an environmental material and/or condition includes a sensing structure and first and second bipolar junction transistors (BJTs). The first BJT has a base that is electrically coupled with the sensing structure and is configured to generate an output signal indicative of a change in stored charge in the sensing structure. The second BJT is configured to amplify the output signal of the first bipolar junction transistor. The first and second BJTs and the sensing structure are monolithically formed a common substrate.
摘要翻译: 用于检测环境材料和/或条件的存在的集成传感器包括感测结构和第一和第二双极结型晶体管(BJT)。 第一BJT具有与感测结构电耦合的基极,并且被配置为产生指示感测结构中存储的电荷的变化的输出信号。 第二BJT被配置为放大第一双极结型晶体管的输出信号。 第一和第二BJT和感测结构是单片形成的共同的基底。
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公开(公告)号:US09478648B2
公开(公告)日:2016-10-25
申请号:US14959877
申请日:2015-12-04
发明人: Yoshihiro Ikura
IPC分类号: H01L29/739 , H01L29/06 , H01L29/10 , H01L29/08 , H01L27/082
CPC分类号: H01L29/7397 , H01L27/0823 , H01L29/0619 , H01L29/0696 , H01L29/0804 , H01L29/0821 , H01L29/1095 , H01L29/402
摘要: A shield electrode is formed above a floating p region in a semiconductor layer and connected to a gate electrode in a trench. The shield electrode is composed of a material having an electrical resistivity lower than that of the gate electrode.
摘要翻译: 屏蔽电极形成在半导体层中的浮动p区上方并与沟槽中的栅电极连接。 屏蔽电极由电阻率低于栅电极的电阻率的材料构成。
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公开(公告)号:US20160284824A1
公开(公告)日:2016-09-29
申请号:US15005195
申请日:2016-01-25
发明人: Nao Nagata
IPC分类号: H01L29/739 , H01L29/08 , H01L29/10 , H01L29/66 , H01L27/082
CPC分类号: H01L29/7397 , H01L21/76895 , H01L23/535 , H01L27/0823 , H01L29/0619 , H01L29/0696 , H01L29/0804 , H01L29/0821 , H01L29/1095 , H01L29/36 , H01L29/407 , H01L29/4236 , H01L29/66348
摘要: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a first trench gate electrode and second and third trench gate electrodes located on both sides of the first trench gate electrode interposed therebetween. In each of a semiconductor layer located between the first and second trench gate electrodes and the semiconductor layer located between the first and third trench gate electrodes, a plurality of p+-type semiconductor regions are formed. The p+-type semiconductor regions are arranged along the extending direction of the first trench gate electrode in plan view to be spaced apart from each other.
摘要翻译: 在半导体器件的性能方面实现了改进。 半导体器件包括位于其间的第一沟槽栅电极的两侧的第一沟槽栅极电极和第二和第三沟槽栅电极。 在位于第一和第二沟槽栅电极之间的半导体层和位于第一和第三沟槽栅电极之间的半导体层的每个中,形成多个p +型半导体区。 p +型半导体区域在平面图中沿着第一沟槽栅电极的延伸方向布置成彼此间隔开。
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公开(公告)号:US09374084B2
公开(公告)日:2016-06-21
申请号:US14934053
申请日:2015-11-05
申请人: Ideal Power Inc.
IPC分类号: H03K17/66 , H02M3/158 , H01L29/739 , H01L29/08 , H01L29/16 , H01L29/737 , H02M1/088 , H02M7/797 , H03K3/012 , H03K17/687 , H01L29/06 , H01L29/10 , H01L29/73 , H02M11/00 , H01L29/732 , H03K17/60 , H01L29/417 , H01L29/423
CPC分类号: H02M3/158 , H01L27/0755 , H01L27/0823 , H01L27/0828 , H01L29/0619 , H01L29/0649 , H01L29/0804 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/16 , H01L29/1604 , H01L29/41708 , H01L29/42304 , H01L29/73 , H01L29/732 , H01L29/7375 , H01L29/7393 , H01L29/7395 , H02M1/088 , H02M3/1582 , H02M7/797 , H02M11/00 , H03K3/012 , H03K17/60 , H03K17/66 , H03K17/687
摘要: Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.
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