Method for forming deep trench isolation for RF devices on SOI
    2.
    发明授权
    Method for forming deep trench isolation for RF devices on SOI 有权
    在SOI上形成RF器件深沟槽隔离的方法

    公开(公告)号:US09349748B2

    公开(公告)日:2016-05-24

    申请号:US14564081

    申请日:2014-12-08

    摘要: A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a SOI substrate having shallow trench isolations (STIs) and transistors formed within and on the second semiconductor substrate, respectively. The method also includes forming a hard mask over the first region and removing the STIs, the transistors, the second semiconductor substrate and the buried insulating layer in the second region using the hard mask as a mask, and forming a capping layer covering the deep trench isolation and the second semiconductor substrate including the transistors.

    摘要翻译: 半导体器件包括具有第一半导体衬底,掩埋绝缘层和形成在第一区域中的第二半导体衬底和设置在第二区域中的深沟槽隔离的堆叠的绝缘体上硅(SOI)衬底。 形成半导体器件的方法包括提供分别形成在第二半导体衬底内和第二半导体衬底上的浅沟槽隔离(STI)和晶体管的SOI衬底。 该方法还包括在第一区域上形成硬掩模,并使用硬掩模作为掩模去除第二区域中的STI,晶体管,第二半导体衬底和埋入绝缘层,并且形成覆盖深沟槽的覆盖层 隔离和包括晶体管的第二半导体衬底。

    METHOD FOR FORMING DEEP TRENCH ISOLATION FOR RF DEVICES ON SOI
    3.
    发明申请
    METHOD FOR FORMING DEEP TRENCH ISOLATION FOR RF DEVICES ON SOI 有权
    用于在SOI上形成RF器件的深度分离隔离的方法

    公开(公告)号:US20150187794A1

    公开(公告)日:2015-07-02

    申请号:US14564081

    申请日:2014-12-08

    摘要: A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a SOI substrate having shallow trench isolations (STIs) and transistors formed within and on the second semiconductor substrate, respectively. The method also includes forming a hard mask over the first region and removing the STIs, the transistors, the second semiconductor substrate and the buried insulating layer in the second region using the hard mask as a mask, and forming a capping layer covering the deep trench isolation and the second semiconductor substrate including the transistors.

    摘要翻译: 半导体器件包括具有第一半导体衬底,掩埋绝缘层和形成在第一区域中的第二半导体衬底和设置在第二区域中的深沟槽隔离的堆叠的绝缘体上硅(SOI)衬底。 形成半导体器件的方法包括提供分别形成在第二半导体衬底内和第二半导体衬底上的浅沟槽隔离(STI)和晶体管的SOI衬底。 该方法还包括在第一区域上形成硬掩模,并使用硬掩模作为掩模去除第二区域中的STI,晶体管,第二半导体衬底和埋入绝缘层,并且形成覆盖深沟槽的覆盖层 隔离和包括晶体管的第二半导体衬底。

    Method to improve cantilever process performance

    公开(公告)号:US09630833B2

    公开(公告)日:2017-04-25

    申请号:US14864851

    申请日:2015-09-24

    发明人: Liang Ni Xinxue Wang

    IPC分类号: H01L21/00 B81C1/00

    CPC分类号: B81C1/0015

    摘要: A method of manufacturing a cantilever structure includes providing a semiconductor substrate, forming a recess in the semiconductor substrate, forming a sacrificial layer in the recess, forming a cantilever structure layer on the semiconductor substrate and the sacrificial layer, performing an etching process to remove a portion of the cantilever structure layer until a surface of the sacrificial layer is exposed to form a cantilever structure and an opening, and removing a portion of the sacrificial layer to form a void below the cantilever structure so that the cantilever structure is suspended in the void. The cantilever structure thus formed has good morphological properties to ensure that the cantilever structure is free of residues at the bottom and has excellent suspension even if the width of the cantilever structure is relatively large.