公开(公告)号：US20230139773A1

公开(公告)日：2023-05-04

申请号：US17974240

申请日：2022-10-26

申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Xinxing BAI ,  Yaping WANG ,  Chunchao FEI

IPC分类号： H01L23/544 ,  H01L21/66 ,  H01L23/31 ,  H01L23/10 ,  H01L21/56 ,  H01L21/822

摘要： A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate, and the substrate includes a scribe line region. The semiconductor structure also includes a device layer over the substrate. The device layer includes multiple devices, an interconnection structure electrically connected to the devices, and a dielectric layer surrounding the devices and the interconnection structure. Further, the device layer includes a passivation layer over the device layer, and an alignment mark in the passivation layer over the scribe line region. The alignment mark includes two or more sub-alignment marks, the two or more sub-alignment marks are arranged along an extension direction of the scribe line region, and adjacent sub-alignment marks of the two or more sub-alignment marks are spaced apart from each other.

公开(公告)号：US11621166B2

公开(公告)日：2023-04-04

申请号：US16878984

申请日：2020-05-20

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Nan Wang

IPC分类号： H01L21/033 ,  H01L21/8238

摘要： A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a substrate, and forming a first core layer on the substrate. The substrate includes a pull-up transistor region. The method also includes forming separately arranged second core layers on the first core layer, and forming a first sacrificial sidewall spacer on a sidewall of a second core layer. A gap is formed between adjacent first sacrificial sidewall spacers over the pull-up transistor region. In addition, the method includes removing the second core layers, and then etching the first core layer using the first sacrificial sidewall spacers as a mask until the substrate is exposed. The gap is transferred to a region between adjacent etched first core layers over the pull-up transistor region. Further, after etching the first core layer, the method includes forming a dielectric layer to fully fill the gap.

公开(公告)号：US11616064B2

公开(公告)日：2023-03-28

申请号：US17019956

申请日：2020-09-14

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  SMIC New Technology Research and Development (Shanghai) Corporation

发明人： Yong Li

IPC分类号： H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/84

摘要： A semiconductor structure is provided. The semiconductor structure includes a base substrate including a semiconductor substrate having a PMOS region and an NMOS region and a plurality of fins on the semiconductor substrate, a gate layer across the plurality of fins by covering portions of top and sidewall surfaces of the fins, a P-type doped epitaxial layer formed in the fins at both sides of the gate layer in the PMOS region, an N-type doped epitaxial layer formed in the fins at both sides of the gate layer in the NMOS region, and an N-region mask layer formed on sidewall surfaces of the N-type doped epitaxial layer and covering the P-type doped epitaxial layer. A portion of the N-type doped epitaxial layer exposed by the N-region mask layer is processed by an N-type dopant segregated Schottky doping process.

公开(公告)号：US11605726B2

公开(公告)日：2023-03-14

申请号：US17226462

申请日：2021-04-09

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Hansu Oh ,  Pengchong Li ,  Xuejie Shi ,  Yiyu Chen ,  Bo Su

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

摘要： A semiconductor structure and a method for forming the same are provided. In one form, a forming method includes: providing a base, a gate structure, a source-drain doping region, and an interlayer dielectric layer; removing the gate structure located in an isolation region to form an isolation opening and expose the top and side walls of a fin located in the isolation region; performing first ion-doping on the fin under the isolation opening to form an isolation doped region, a doping type of the isolation doped region being different from a doping type of the source-drain doping region; and filling the isolation opening with an isolation structure after the doping, the isolation structure straddling the fin of the isolation region. In embodiments and implementations of the present disclosure, the isolation doped region is formed, a doping concentration of inversion ions in the fin of the isolation region can thus be increased, and a barrier of a P-N junction formed by the source-drain doping region and the fin of the isolation region can be increased accordingly, to prevent the device from generating a conduction current in the fin of the isolation region during operation, thereby implementing isolation between the fin of the isolation region and the fin of other regions. Moreover, there is no need to perform a fin cut process. Hence the fin is made into a continuous structure, which helps prevent stress relief in the fin.

公开(公告)号：US11581320B2

公开(公告)日：2023-02-14

申请号：US17237648

申请日：2021-04-22

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Fei Zhou

IPC分类号： H01L27/11 ,  H01L27/088 ,  H01L29/66 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/8234

摘要： Semiconductor device is provided. The semiconductor device includes a base substrate including a first region, a second region, and a third region arranged along a first direction, a first doped layer in the base substrate at the first region and a second doped layer in the base substrate at the third region, a first gate structure on the base substrate at the second region, a first dielectric layer on the base substrate coving the first doped layer, the second doped layer, and sidewalls of the first gate structure, first trenches in the first dielectric layer at the first region and the third region respectively, a first conductive layer in the first trenches, a second conductive layer on a surface of the first conductive layer at the second sub-regions after forming the first conductive layer, and a third conductive layer on the contact region of the first gate structure.

公开(公告)号：US11545552B2

公开(公告)日：2023-01-03

申请号：US17104218

申请日：2020-11-25

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Nan Wang

IPC分类号： H01L29/417 ,  H01L21/033 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40

摘要： A semiconductor structure and a method for forming the same are provided. One form of a forming method includes: providing a base, the base including a device region and a dummy device region, the base including an isolation layer, gate structures located on the isolation layer, a first mask layer located on the gate structures, a source-drain plug located between the gate structures and on the isolation layer, and a second mask layer located on the source-drain plug. In implementations of the present disclosure, the first mask layer and the second mask layer on the dummy device region are separately removed. Correspondingly, the first opening and the second opening respectively expose the gate structures and the source-drain plug in the dummy device region. The gate structures exposed by the first opening and the source-drain plug exposed by the second opening are removed in the same step. The gate groove at the bottom of the first opening and the source-drain groove at the bottom of the second opening are formed at the same time. Correspondingly, a dielectric layer may be formed in the gate groove and the source-drain groove in the same step. The dielectric layer may block the gate structures and the source-drain plug at the same time. This is advantageous for simplifying the formation process of the semiconductor structure.

公开(公告)号：US11545496B2

公开(公告)日：2023-01-03

申请号：US17032820

申请日：2020-09-25

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Yong Li

IPC分类号： H01L29/165 ,  H01L27/11 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  G11C11/412 ,  H01L29/78

摘要： An SRAM (static random access memory) includes a semiconductor substrate; a plurality of PD transistors, each including a first fin structure formed on the semiconductor substrate, a PD gate structure formed across the first fin structure and covering a portion of a top and sidewall surfaces of the first fin structure, and a first source/drain doped layer formed in the first fin structure on both sides of the PD gate structure; a plurality of adjacent transistors, each including a second fin structure formed on the semiconductor substrate and a second source/drain doped layer formed in the second fin structure; an isolation layer, formed on the semiconductor substrate; a fin sidewall film, formed on the isolation layer and covering sidewall surfaces of each PD gate structure; and a first PD dielectric layer, formed on the isolation layer and covering sidewall surfaces of the first source/drain doped layer.

公开(公告)号：US11545396B2

公开(公告)日：2023-01-03

申请号：US16938269

申请日：2020-07-24

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Deyan Chen ,  Mao Li ,  Dae-Sub Jung

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

摘要： A method for forming a semiconductor structure includes providing a substrate, including a first region and a second region; forming a plurality of fin structures on the substrate; forming an isolation structure between adjacent fin structures; forming a mask layer over the substrate and the plurality of fin structures; forming an opening by removing a portion of the mask layer formed in the first region; removing a portion of the isolation structure exposed in the opening by using a remaining portion of the mask layer as a mask; removing the remaining portion of the mask layer; and forming a gate structure across the plurality of fin structures. The gate structure covers the first region.

公开(公告)号：US11508848B2

公开(公告)日：2022-11-22

申请号：US17093877

申请日：2020-11-10

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION ,  SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION

发明人： Meng Zhao

IPC分类号： H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/812 ,  H01L29/165 ,  H01L21/28 ,  H01L29/49

摘要： The present disclosure teaches semiconductor devices and methods for manufacturing the same. Implementations of the semiconductor device may include: a semiconductor substrate; a semiconductor fin positioned on the semiconductor substrate; and a gate structure positioned on the semiconductor fin, where the gate structure includes a gate dielectric layer on a part of a surface of the semiconductor fin and a gate on the gate dielectric layer; where the gate includes a metal gate layer on the gate dielectric layer and a semiconductor layer on a side surface of at least one side of the metal gate layer; and where the semiconductor layer includes a dopant, where a conductivity type of the dopant is the opposite of a conductivity type of the semiconductor fin. The present disclosure can improve a work function of the device, thereby improving a current characteristic of the device during a working process, reducing the short channel effect (SCE), and lowering a leakage current.

公开(公告)号：US11508726B2

公开(公告)日：2022-11-22

申请号：US17189611

申请日：2021-03-02

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Jin Jisong

IPC分类号： H01L29/40 ,  H01L27/092 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3105 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417

摘要： A semiconductor structure and a method for forming the same are provided. In one form, the method includes: providing a base, a gate structure being formed on the base, a source/drain doped layer being formed within the base on both sides of the gate structure, and an initial dielectric layer being formed on the base exposed from the gate structure, the initial dielectric layer covering a top of the gate structure, and a source/drain contact plug electrically connected to the source/drain doped layer being formed within the initial dielectric layer on the top of the source/drain doped layer; removing a portion of a thickness of the initial dielectric layer to form a dielectric layer exposing a portion of a side wall of the source/drain contact plug; forming an etch stop layer on at least the side wall of source/drain contact plug exposed from the dielectric layer; etching the dielectric layer on the top of the gate structure using etch stop layers on side walls of adjacent source/drain contact plugs as lateral stop positions, to form a gate contact exposing the top of the gate structure; forming, within the gate contact, a gate contact plug electrically connected to the gate structure. Implementations of the present disclosure facilitate enlargement of a process window for forming a contact over active gate.