专利检索 ap:("SEONG-HWAN JEON" OR "KYUNG-SOO HA" OR "JIN-SEOK HEO" OR "IN-DAL SONG" OR "JUNG-HWAN CHOI") AND inv:"KYUNG-SOO HA" 第 1 页

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发明申请
DATA ALIGNMENT CIRCUIT OF A SEMICONDUCTOR MEMORY DEVICE, A SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF ALIGNING DATA IN A SEMICONDUCTOR MEMORY DEVICE 审中-公开

公开(公告)号：US20180174636A1

公开(公告)日：2018-06-21

申请号：US15787101

申请日：2017-10-18

申请人： SEONG-HWAN JEON , KYUNG-SOO HA , JIN-SEOK HEO , IN-DAL SONG , JUNG-HWAN CHOI

发明人： SEONG-HWAN JEON , KYUNG-SOO HA , JIN-SEOK HEO , IN-DAL SONG , JUNG-HWAN CHOI

IPC分类号： G11C11/402 , G11C11/22 , G11C7/22

CPC分类号： G11C11/4023 , G11C7/1012 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C11/2293 , G11C11/4093

摘要： A data alignment circuit of a semiconductor memory device including: a data sampling circuit configured to receive a data sequence and an internal data strobe signal, wherein the data sampling circuit samples the data sequence based on the internal data strobe signal to generate first and second data sequences; a division circuit configured to receive a clock signal and the internal data strobe signal, divide the clock signal to produce a divided clock signal and output an alignment control signal by sampling the divided clock signal based on the internal data strobe signal; and a data alignment block configured to receive the first and second data sequences, and the alignment control signal, and align the first and second data sequences in parallel to output internal data.