Abstract:
A method is provided for transmitting signals on a multi-conductor cable (12) formed from a plurality of conductors (1-7) surrounded by an armor (10), the plurality of conductors having a central conductor (7) surrounded by a first peripheral layer of conductors (1-6) with an even number of conductors symmetrically arranged around the central conductor. The two following transmission modes are carried out simultaneously: a common mode (TX1) that uses the central conductor (7) with a return on the armor (10), for transmitting a first signal (s1); and a differential mode (TX2) between a first path comprising all odd rank conductors (1,3,5) of the peripheral layer and a second path comprising all even rank conductors (2,4,6) of the peripheral layer, for transmitting a second signal (s2).
Abstract:
A method is provided for transmitting signals on a multi-conductor cable (12) formed from a plurality of conductors (1-7) surrounded by an armor (10), the plurality of conductors having a central conductor (7) surrounded by a first peripheral layer of conductors (1-6) with an even number of conductors symmetrically arranged around the central conductor. The two following transmission modes are carried out simultaneously: a common mode (TX1) that uses the central conductor (7) with a return on the armor (10), for transmitting a first signal (s1); and a differential mode (TX2) between a first path comprising all odd rank conductors (1,3,5) of the peripheral layer and a second path comprising all even rank conductors (2,4,6) of the peripheral layer, for transmitting a second signal (s2).
Abstract:
A system and method for adjusting a clock signal of a seismic data acquisition system. The system includes a data acquisition device having an oscillator that generates a clock signal; a clock adjustment module that receives a time reference signal and the clock signal and outputs an adjusted clock signal; and an analog-to-digital convertor configured to transform analog data into digital data having a sampling rate (FDATA). A sampling frequency (fADC) of the analog-to-digital convertor is selected to be at least twice the sampling rate (FDATA).