公开(公告)号：US20030017666A1

公开(公告)日：2003-01-23

申请号：US10247177

申请日：2002-09-19

Applicant: SGS-Thomson Microelectronics S.r.l.

Inventor： Giuseppe Queirolo ,  Giovanni Ferroni

IPC: H01L021/8238

CPC classification number: H01L28/82 ,  C23C16/24 ,  H01L21/28273 ,  H01L21/28556 ,  H01L21/3205

Abstract: The electrical performance of a dielectric film for capacitive coupling in an integrated structure is enhanced by forming the polycrystalline electrically conductive layer coupled with the dielectric film substantially unigranular over the coupling area, commonly to be defined by patterning the stacked dielectric and conductive layers. The process forms a polycrystalline silicon film having exceptionally large grains of a size on the same order of magnitude as the dimensions of the patterned details. These exceptionally large grains are obtained by preventing the formation of nullprecursor nucleinull of subsequent grain formation and growth at the deposition interface with the dielectric that are apparently formed during the first instants of silicon CVD deposition and by successively growing the crystallites at a sufficiently low annealing temperature.