公开(公告)号：US20030017666A1

公开(公告)日：2003-01-23

申请号：US10247177

申请日：2002-09-19

Applicant: SGS-Thomson Microelectronics S.r.l.

Inventor： Giuseppe Queirolo ,  Giovanni Ferroni

IPC: H01L021/8238

CPC classification number: H01L28/82 ,  C23C16/24 ,  H01L21/28273 ,  H01L21/28556 ,  H01L21/3205

Abstract: The electrical performance of a dielectric film for capacitive coupling in an integrated structure is enhanced by forming the polycrystalline electrically conductive layer coupled with the dielectric film substantially unigranular over the coupling area, commonly to be defined by patterning the stacked dielectric and conductive layers. The process forms a polycrystalline silicon film having exceptionally large grains of a size on the same order of magnitude as the dimensions of the patterned details. These exceptionally large grains are obtained by preventing the formation of nullprecursor nucleinull of subsequent grain formation and growth at the deposition interface with the dielectric that are apparently formed during the first instants of silicon CVD deposition and by successively growing the crystallites at a sufficiently low annealing temperature.

公开(公告)号：US20020140021A1

公开(公告)日：2002-10-03

申请号：US10158706

申请日：2002-05-30

Applicant: SGS-THOMSON MICROELECTRONICS S.R.L.

Inventor： Paolo Cappelletti

IPC: H01L029/76

CPC classification number: H01L21/28185 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/2822 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/49 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518

Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.

Abstract translation: 包括至少一个浮置栅极晶体管并且在半导体衬底上实现的类型的非易失性存储单元包括源极区和漏极区，该沟道区由覆盖有栅极氧化物的薄层 。 栅极氧化物从衬底隔离浮栅区域。 浮栅区域耦合到控制栅极端子。 存储单元的浮置栅极区域在半导体衬底和栅极氧化物层之间形成第一势垒，并且在浮置栅极区域和栅极氧化物之间形成第二个不同的势垒。

公开(公告)号：US20040173840A1

公开(公告)日：2004-09-09

申请号：US10792308

申请日：2004-03-03

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Paolo Cappelletti

IPC: H01L029/788

CPC classification number: H01L21/28185 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/2822 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/49 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518

Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.