公开(公告)号：US11640923B2

公开(公告)日：2023-05-02

申请号：US17485189

申请日：2021-09-24

Applicant: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION

Inventor： Tianpeng Guan ,  Jianghua Leng ,  Zhonghua Li ,  Yufeng Chen ,  Nan Li ,  Ming Tian

IPC: H01L21/762

Abstract: The present application provides a method for manufacturing FDSOI devices. The method includes steps of: providing a semiconductor structure which comprises a silicon substrate, a buried oxide layer on the silicon substrate, a silicon-on-insulator layer on the buried oxide layer; and a hard mask layer on the silicon-on-insulator layer; performing spin coating of a photoresist on the hard mask layer to form a bulk silicon region; performing plasma anisotropic etching on the bulk silicon region to open a part of the buried oxide layer, and then performing isotropic etching, so that the silicon-on-insulator layer shrinks in the horizontal direction; performing plasma anisotropic etching to etch through the buried oxide layer to form a bulk silicon region trench; performing silicon epitaxial growth in the bulk silicon region trench. The silicon-on-insulator layer is still shrinks after the bulk silicon region trench is formed, as the result, there is no bump on the surface of the silicon-on-insulator layer, thus the process window becomes controllable.

公开(公告)号：US20230126031A1

公开(公告)日：2023-04-27

申请号：US18086326

申请日：2022-12-21

Applicant: Shanghai Huali Integrated Circuit Corporation

Inventor： Zhonghua Li ,  Runling Li ,  Nan Li ,  Jianghua Leng ,  Tianpeng Guan

IPC: H01L29/78 ,  H01L29/26 ,  H01L29/06 ,  H01L21/762

Abstract: FDSOI device fabrication method is disclosed. The method comprises: disposing a buried oxide layer on the silicon substrate; disposing a SiGe channel on the buried oxide layer, disposing a nitrogen passivation layer on the SiGe channel layer; disposing a metal gate on the nitrogen passivation layer, and attaching sidewalls to sides of the metal gate; and disposing source and drain regions on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the gate channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

公开(公告)号：US11569385B2

公开(公告)日：2023-01-31

申请号：US17107375

申请日：2020-11-30

Applicant: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION

Inventor： Zhonghua Li ,  Runling Li ,  Nan Li ,  Jianghua Leng ,  Tianpeng Guan

IPC: H01L29/78 ,  H01L29/26 ,  H01L29/06 ,  H01L21/762

Abstract: An FDSOI device and fabrication method are disclosed. The device comprises: a buried oxide layer disposed on the silicon substrate; a SiGe channel disposed on the buried oxide layer, a nitrogen passivation layer disposed on the SiGe channel layer; a metal gate disposed on the nitrogen passivation layer, and sidewalls attached to sides of the metal gate; and a source and a drain regions disposed on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

公开(公告)号：US11855212B2

公开(公告)日：2023-12-26

申请号：US18086326

申请日：2022-12-21

Applicant: Shanghai Huali Integrated Circuit Corporation

Inventor： Zhonghua Li ,  Runling Li ,  Nan Li ,  Jianghua Leng ,  Tianpeng Guan

IPC: H01L29/78 ,  H01L29/26 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/7848 ,  H01L21/76243 ,  H01L29/0638 ,  H01L29/263

Abstract: FDSOI device fabrication method is disclosed. The method comprises: disposing a buried oxide layer on the silicon substrate; disposing a SiGe channel on the buried oxide layer, disposing a nitrogen passivation layer on the SiGe channel layer; disposing a metal gate on the nitrogen passivation layer, and attaching sidewalls to sides of the metal gate; and disposing source and drain regions on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the gate channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

公开(公告)号：US11069532B2

公开(公告)日：2021-07-20

申请号：US16704153

申请日：2019-12-05

Applicant: Shanghai Huali Integrated Circuit Corporation

Inventor： Zhonghua Li

IPC: H01L21/283 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

Abstract: The invention discloses a method for manufacturing nickel silicide. The method comprises: Step 1: providing a semiconductor substrate, wherein the semiconductor substrate has an exposed silicon surface which is a formation region of nickel silicide; Step 2: carrying out pre-amorphization ion implantation to form an amorphous layer in the formation region of the nickel silicide, wherein an implantation source of the pre-amorphization ion implantation is xenon; and Step 3: forming the nickel silicide in the formation region of the nickel silicide by self-alignment. Xenon which is a non-radioactive inert gas with the maximum mass is adopted to optimize the uniformity of an interface layer between the amorphous layer and silicon, so that the uniformity of the ohm contact resistance of the nickel silicide is improved.

公开(公告)号：US20210050217A1

公开(公告)日：2021-02-18

申请号：US16704153

申请日：2019-12-05

Applicant: Shanghai Huali Integrated Circuit Corporation

Inventor： Zhonghua Li

IPC: H01L21/283 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

Abstract: The invention discloses a method for manufacturing nickel silicide. The method comprises: Step 1: providing a semiconductor substrate, wherein the semiconductor substrate has an exposed silicon surface which is a formation region of nickel silicide; Step 2: carrying out pre-amorphization ion implantation to form an amorphous layer in the formation region of the nickel silicide, wherein an implantation source of the pre-amorphization ion implantation is xenon; and Step 3: forming the nickel silicide in the formation region of the nickel silicide by self-alignment. Xenon which is a non-radioactive inert gas with the maximum mass is adopted to optimize the uniformity of an interface layer between the amorphous layer and silicon, so that the uniformity of the ohm contact resistance of the nickel silicide is improved.

公开(公告)号：US11018219B2

公开(公告)日：2021-05-25

申请号：US16704335

申请日：2019-12-05

Applicant: Shanghai Huali Integrated Circuit Corporation

Inventor： Zhonghua Li

IPC: H01L29/06 ,  H01L21/266 ,  H01L21/324 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: The invention discloses a P-type MOSFET, a channel region consisting of an N-well is formed in the semiconductor substrate covered with a gate structure; the N-well is formed by overlaying an annealed phosphorus-implanted region, an annealed first arsenic-implanted region and an annealed second arsenic-implanted region, and the first arsenic-implanted region and the second arsenic-implanted region are overlaid to form a threshold voltage regulation region; the implantation depth of the first arsenic-implanted region is greater than that of the second arsenic-implanted region; and an amorphous layer is formed by the first arsenic-implanted region on the semiconductor substrate to improve the implantation uniformity of the second arsenic-implanted region and to decrease the peak surface doping concentration of the second arsenic-implanted region located on the surface of the semiconductor substrate. The invention further discloses a method for manufacturing a P-type MOSFET. The invention can reduce the flicker noises of a device.

公开(公告)号：US10978360B2

公开(公告)日：2021-04-13

申请号：US16702924

申请日：2019-12-04

Applicant: Shanghai Huali Integrated Circuit Corporation

Inventor： Zhonghua Li

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/28 ,  H01L23/544 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311

Abstract: A PNA temperature monitoring method comprises: Step 1, forming zero mark layer patterns on a tested silicon substrate; Step 2, forming a nitrogen-doped gate oxide by the following process: growing an oxide layer, doping the oxide layer with nitrogen, and carrying out PNA; Step 3, forming overlay layer patterns, and overlaying the overlay layer patterns and the corresponding zero mark layer patterns to form monitoring structures; and Step 4, measuring overlay values of the overlay layer patterns and the corresponding zero mark layer patterns of the monitoring structures, and regulating a PNA temperature according to the measured overlay values. By adoption of the method, the influence of the PNA temperature on a gate oxide in a two-dimensional plane can be monitored, and then the PNA temperature can be regulated to increase product yield.

公开(公告)号：US20210043725A1

公开(公告)日：2021-02-11

申请号：US16704335

申请日：2019-12-05

Applicant: Shanghai Huali Integrated Circuit Corporation

Inventor： Zhonghua Li

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/266 ,  H01L21/324

Abstract: The invention discloses a P-type MOSFET, a channel region consisting of an N-well is formed in the semiconductor substrate covered with a gate structure; the N-well is formed by overlaying an annealed phosphorus-implanted region, an annealed first arsenic-implanted region and an annealed second arsenic-implanted region, and the first arsenic-implanted region and the second arsenic-implanted region are overlaid to form a threshold voltage regulation region; the implantation depth of the first arsenic-implanted region is greater than that of the second arsenic-implanted region; and an amorphous layer is formed by the first arsenic-implanted region on the semiconductor substrate to improve the implantation uniformity of the second arsenic-implanted region and to decrease the peak surface doping concentration of the second arsenic-implanted region located on the surface of the semiconductor substrate. The invention further discloses a method for manufacturing a P-type MOSFET. The invention can reduce the flicker noises of a device.

公开(公告)号：US20210028072A1

公开(公告)日：2021-01-28

申请号：US16702924

申请日：2019-12-04

Applicant: Shanghai Huali Integrated Circuit Corporation

Inventor： Zhonghua Li

IPC: H01L21/66 ,  H01L21/28 ,  H01L23/544

Abstract: A PNA temperature monitoring method comprises: Step 1, forming zero mark layer patterns on a tested silicon substrate; Step 2, forming a nitrogen-doped gate oxide by the following process: growing an oxide layer, doping the oxide layer with nitrogen, and carrying out PNA; Step 3, forming overlay layer patterns, and overlaying the overlay layer patterns and the corresponding zero mark layer patterns to form monitoring structures; and Step 4, measuring overlay values of the overlay layer patterns and the corresponding zero mark layer patterns of the monitoring structures, and regulating a PNA temperature according to the measured overlay values. By adoption of the method, the influence of the PNA temperature on a gate oxide in a two-dimensional plane can be monitored, and then the PNA temperature can be regulated to increase product yield.