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    Double Control Gate Semi-Floating Gate Transistor and Method for Preparing the Same
    1.
    发明申请
    Double Control Gate Semi-Floating Gate Transistor and Method for Preparing the Same 有权

    公开(公告)号：US20220238671A1

    公开(公告)日：2022-07-28

    申请号：US17400657

    申请日：2021-08-12

    Applicant: Shanghai Huali Integrated Circuit Corporation

    Inventor： Heng Liu ,  Zhigang Yang ,  Jianghua Leng ,  Tianpeng Guan

    IPC: H01L29/423 ,  H01L29/66 ,  H01L29/788

    Abstract: The present application provides a double control gate semi-floating gate transistor and a method for preparing the same. A lightly doped well region provided with a U-shaped groove is located on a substrate; one part of a floating gate oxide layer covers sidewalls and a bottom of the U-shaped groove, the other part covers the lightly doped well region on one side, and the floating gate oxide layer covering the lightly doped well region; a floating gate polysilicon layer is filled in the U-shaped groove and covers the floating gate oxide layer; a polysilicon control gate stack includes a polysilicon control gate oxide layer on the floating gate polysilicon layer and a polysilicon control gate polysilicon layer on the polysilicon control gate oxide layer; a metal control gate stack includes a high-K dielectric layer and a metal gate.

    FDSOI device structure and preparation method thereof
    2.
    发明授权
    FDSOI device structure and preparation method thereof 有权

    公开(公告)号：US11855212B2

    公开(公告)日：2023-12-26

    申请号：US18086326

    申请日：2022-12-21

    Applicant: Shanghai Huali Integrated Circuit Corporation

    Inventor： Zhonghua Li ,  Runling Li ,  Nan Li ,  Jianghua Leng ,  Tianpeng Guan

    IPC: H01L29/78 ,  H01L29/26 ,  H01L29/06 ,  H01L21/762

    CPC classification number: H01L29/7848 ,  H01L21/76243 ,  H01L29/0638 ,  H01L29/263

    Abstract: FDSOI device fabrication method is disclosed. The method comprises: disposing a buried oxide layer on the silicon substrate; disposing a SiGe channel on the buried oxide layer, disposing a nitrogen passivation layer on the SiGe channel layer; disposing a metal gate on the nitrogen passivation layer, and attaching sidewalls to sides of the metal gate; and disposing source and drain regions on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the gate channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

    Semi-floating gate device
    3.
    发明授权
    Semi-floating gate device 有权

    公开(公告)号：US11955524B2

    公开(公告)日：2024-04-09

    申请号：US17828299

    申请日：2022-05-31

    Applicant: Shanghai Huali Integrated Circuit Corporation

    Inventor： Heng Liu ,  Jianghua Leng ,  Zhigang Yang ,  Tianpeng Guan

    IPC: H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H10B41/30 ,  H10B41/40

    CPC classification number: H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30 ,  H10B41/40

    Abstract: The present application discloses a semi-floating gate device. A floating gate structure covers a selected area of a first well region and is used to form a conductive channel. The floating gate structure further covers a surface of a lightly doped drain region, and a floating gate material layer and the lightly doped drain region contact at a dielectric layer window to form a PN structure. A source region is self-aligned with a first side surface of the floating gate structure. A first control gate is superposed on a top of the floating gate structure. A second control gate is disposed on a surface of the lightly doped drain region between the drain region and a second side surface of the floating gate structure. The first control gate and the second control gate are isolated by an inter-gate dielectric layer.

    Semi-Floating Gate Device
    4.
    发明申请
    Semi-Floating Gate Device 有权

    公开(公告)号：US20220384596A1

    公开(公告)日：2022-12-01

    申请号：US17828299

    申请日：2022-05-31

    Applicant: Shanghai Huali Integrated Circuit Corporation

    Inventor： Heng Liu ,  Jianghua Leng ,  Zhigang Yang ,  Tianpeng Guan

    IPC: H01L29/423 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/66 ,  H01L29/788

    Abstract: The present application discloses a semi-floating gate device. A floating gate structure covers a selected area of a first well region and is used to form a conductive channel. The floating gate structure further covers a surface of a lightly doped drain region, and a floating gate material layer and the lightly doped drain region contact at a dielectric layer window to form a PN structure. A source region is self-aligned with a first side surface of the floating gate structure. A first control gate is superposed on a top of the floating gate structure. A second control gate is disposed on a surface of the lightly doped drain region between the drain region and a second side surface of the floating gate structure. The first control gate and the second control gate are isolated by an inter-gate dielectric layer.

    Method for manufacturing FDSOI
    6.
    发明授权
    Method for manufacturing FDSOI 有权

    公开(公告)号：US11640923B2

    公开(公告)日：2023-05-02

    申请号：US17485189

    申请日：2021-09-24

    Applicant: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION

    Inventor： Tianpeng Guan ,  Jianghua Leng ,  Zhonghua Li ,  Yufeng Chen ,  Nan Li ,  Ming Tian

    IPC: H01L21/762

    Abstract: The present application provides a method for manufacturing FDSOI devices. The method includes steps of: providing a semiconductor structure which comprises a silicon substrate, a buried oxide layer on the silicon substrate, a silicon-on-insulator layer on the buried oxide layer; and a hard mask layer on the silicon-on-insulator layer; performing spin coating of a photoresist on the hard mask layer to form a bulk silicon region; performing plasma anisotropic etching on the bulk silicon region to open a part of the buried oxide layer, and then performing isotropic etching, so that the silicon-on-insulator layer shrinks in the horizontal direction; performing plasma anisotropic etching to etch through the buried oxide layer to form a bulk silicon region trench; performing silicon epitaxial growth in the bulk silicon region trench. The silicon-on-insulator layer is still shrinks after the bulk silicon region trench is formed, as the result, there is no bump on the surface of the silicon-on-insulator layer, thus the process window becomes controllable.

    FDSOI DEVICE STRUCTURE AND PREPARATION METHOD THEREOF
    7.
    发明申请
    FDSOI DEVICE STRUCTURE AND PREPARATION METHOD THEREOF 有权

    公开(公告)号：US20230126031A1

    公开(公告)日：2023-04-27

    申请号：US18086326

    申请日：2022-12-21

    Applicant: Shanghai Huali Integrated Circuit Corporation

    Inventor： Zhonghua Li ,  Runling Li ,  Nan Li ,  Jianghua Leng ,  Tianpeng Guan

    IPC: H01L29/78 ,  H01L29/26 ,  H01L29/06 ,  H01L21/762

    Abstract: FDSOI device fabrication method is disclosed. The method comprises: disposing a buried oxide layer on the silicon substrate; disposing a SiGe channel on the buried oxide layer, disposing a nitrogen passivation layer on the SiGe channel layer; disposing a metal gate on the nitrogen passivation layer, and attaching sidewalls to sides of the metal gate; and disposing source and drain regions on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the gate channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

    FDSOI device structure and preparation method thereof
    8.
    发明授权
    FDSOI device structure and preparation method thereof 有权

    公开(公告)号：US11569385B2

    公开(公告)日：2023-01-31

    申请号：US17107375

    申请日：2020-11-30

    Applicant: SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION

    Inventor： Zhonghua Li ,  Runling Li ,  Nan Li ,  Jianghua Leng ,  Tianpeng Guan

    IPC: H01L29/78 ,  H01L29/26 ,  H01L29/06 ,  H01L21/762

    Abstract: An FDSOI device and fabrication method are disclosed. The device comprises: a buried oxide layer disposed on the silicon substrate; a SiGe channel disposed on the buried oxide layer, a nitrogen passivation layer disposed on the SiGe channel layer; a metal gate disposed on the nitrogen passivation layer, and sidewalls attached to sides of the metal gate; and a source and a drain regions disposed on the nitrogen passivation layer at both sides of the metal gate, wherein the source and drain regions are built in a raised SiGe layer. The stack structure of the SiGe layer and the nitrogen passivation layer forms the channel. This stack structure avoids the low stress of the silicon channel in the conventional device. In addition, it prevents the Ge diffusion from the SiGe channel to the gate dielectric in the conventional device. Thereby the invention improves reliability and performance of the device.

    Double control gate semi-floating gate transistor and method for preparing the same
    10.
    发明授权
    Double control gate semi-floating gate transistor and method for preparing the same 有权

    公开(公告)号：US11637187B2

    公开(公告)日：2023-04-25

    申请号：US17400657

    申请日：2021-08-12

    Applicant: Shanghai Huali Integrated Circuit Corporation

    Inventor： Heng Liu ,  Zhigang Yang ,  Jianghua Leng ,  Tianpeng Guan

    IPC: H01L29/788 ,  H01L29/423 ,  H01L29/66

    Abstract: The present application provides a double control gate semi-floating gate transistor and a method for preparing the same. A lightly doped well region provided with a U-shaped groove is located on a substrate; one part of a floating gate oxide layer covers sidewalls and a bottom of the U-shaped groove, the other part covers the lightly doped well region on one side, and the floating gate oxide layer covering the lightly doped well region; a floating gate polysilicon layer is filled in the U-shaped groove and covers the floating gate oxide layer; a polysilicon control gate stack includes a polysilicon control gate oxide layer on the floating gate polysilicon layer and a polysilicon control gate polysilicon layer on the polysilicon control gate oxide layer; a metal control gate stack includes a high-K dielectric layer and a metal gate.

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