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公开(公告)号:US11790867B2
公开(公告)日:2023-10-17
申请号:US18076433
申请日:2022-12-07
Applicant: Sharp Kabushiki Kaisha
Inventor: Tetsuo Kikuchi , Hideki Kitagawa , Hajime Imai , Toshikatsu Itoh , Masahiko Suzuki , Teruyuki Ueda , Kengo Hara , Setsuji Nishimiya , Tohru Daitoh
IPC: G09G3/36 , G02F1/1362 , H10K59/00 , H10K59/123 , H01L27/12
CPC classification number: G09G3/3648 , G02F1/136213 , H10K59/00 , H10K59/123 , H01L27/1214
Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.
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公开(公告)号:US11551629B2
公开(公告)日:2023-01-10
申请号:US17724781
申请日:2022-04-20
Applicant: Sharp Kabushiki Kaisha
Inventor: Tetsuo Kikuchi , Hideki Kitagawa , Hajime Imai , Toshikatsu Itoh , Masahiko Suzuki , Teruyuki Ueda , Kengo Hara , Setsuji Nishimiya , Tohru Daitoh
IPC: G09G3/36 , G02F1/1362 , H01L27/32 , H01L27/12
Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.
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公开(公告)号:US10741696B2
公开(公告)日:2020-08-11
申请号:US16336481
申请日:2017-09-21
Applicant: Sharp Kabushiki Kaisha
Inventor: Masahiko Suzuki , Hajime Imai , Hideki Kitagawa , Tetsuo Kikuchi , Setsuji Nishimiya , Teruyuki Ueda , Kengo Hara , Tohru Daitoh , Toshikatsu Itoh
IPC: H01L29/786 , G02F1/1343 , G02F1/1345 , G02F1/1368 , H01L21/02 , H01L27/12 , H01L29/24 , H01L29/66 , G02F1/1362
Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, the semiconductor layer includes a layered structure including a first oxide semiconductor layer including In and Zn, in which an atomic ratio of In with respect to all metallic elements included in the first oxide semiconductor layer is higher than an atomic ratio of Zn, a second oxide semiconductor layer including In and Zn, in which an atomic ratio of Zn with respect to all metallic elements included in the second oxide semiconductor layer is higher than an atomic ratio of In, and an intermediate oxide semiconductor layer arranged between the first oxide semiconductor layer and the second oxide semiconductor layer, and the first and second oxide semiconductor layers are crystalline oxide semiconductor layers, and the intermediate oxide semiconductor layer is an amorphous oxide semiconductor layer, and the first oxide semiconductor layer is arranged nearer to the gate insulating layer than the second oxide semiconductor layer.
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公开(公告)号:US10593809B2
公开(公告)日:2020-03-17
申请号:US16182643
申请日:2018-11-07
Applicant: Sharp Kabushiki Kaisha
Inventor: Masahiko Suzuki , Tohru Daitoh , Hajime Imai , Tetsuo Kikuchi , Setsuji Nishimiya , Teruyuki Ueda , Kengo Hara
IPC: H01L29/10 , H01L21/00 , H01L29/786
Abstract: A semiconductor device includes a substrate and an oxide semiconductor TFT including an oxide semiconductor layer supported by the substrate and having a multilayer structure including a protective oxide semiconductor layer and a channel oxide semiconductor layer disposed closer to the substrate than the protective oxide semiconductor layer, an upper insulating layer on the oxide semiconductor layer, an upper gate electrode disposed on the upper insulating layer, an interlayer insulating layer covering the oxide semiconductor layer and the upper gate electrode, and first and second electrodes electrically connected to the oxide semiconductor layer, wherein a first opening extends through at least the interlayer insulating layer and the protective oxide semiconductor layer, and exposes a portion of the channel oxide semiconductor layer, and the first electrode is disposed on the interlayer insulating layer and within the first opening, and is in direct contact with, within the first opening, the portion.
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公开(公告)号:US12034010B2
公开(公告)日:2024-07-09
申请号:US18119624
申请日:2023-03-09
Applicant: Sharp Kabushiki Kaisha
Inventor: Masahiko Suzuki , Tetsuo Kikuchi , Hideki Kitagawa , Setsuji Nishimiya , Kengo Hara , Hitoshi Takahata , Tohru Daitoh
IPC: H01L27/12 , H01L29/786 , H01L29/00
CPC classification number: H01L27/124 , H01L27/1222 , H01L27/1225 , H01L27/1237 , H01L27/127 , H01L29/7869 , H01L29/78696
Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.
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公开(公告)号:US11322105B2
公开(公告)日:2022-05-03
申请号:US17401396
申请日:2021-08-13
Applicant: Sharp Kabushiki Kaisha
Inventor: Tetsuo Kikuchi , Hideki Kitagawa , Hajime Imai , Toshikatsu Itoh , Masahiko Suzuki , Teruyuki Ueda , Kengo Hara , Setsuji Nishimiya , Tohru Daitoh
IPC: G09G3/36 , G02F1/1362 , H01L27/32 , H01L27/12
Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.
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公开(公告)号:US11296126B2
公开(公告)日:2022-04-05
申请号:US16830313
申请日:2020-03-26
Applicant: Sharp Kabushiki Kaisha
Inventor: Hajime Imai , Tohru Daitoh , Tetsuo Kikuchi , Masamitsu Yamanaka , Yoshihito Hara , Tatsuya Kawasaki , Masahiko Suzuki , Setsuji Nishimiya
IPC: H01L27/12 , H01L29/24 , H01L29/417 , H01L29/786 , H01L21/02 , H01L21/465 , H01L29/66 , G02F1/1368 , G02F1/1362 , G02F1/1343
Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.
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公开(公告)号:US11189645B2
公开(公告)日:2021-11-30
申请号:US16497505
申请日:2018-03-26
Applicant: Sharp Kabushiki Kaisha
Inventor: Hideki Kitagawa , Hajime Imai , Toshikatsu Itoh , Tetsuo Kikuchi , Masahiko Suzuki , Teruyuki Ueda , Kengo Hara , Setsuji Nishimiya , Tohru Daitoh
IPC: H01L27/12 , G02F1/1362
Abstract: There is provided a high-definition active matrix substrate while suppressing an occurrence of pixel defects. The active matrix substrate includes a first semiconductor film corresponding to one of two sub-pixels adjacent to each other in a row direction, a second semiconductor film corresponding to the other of two sub-pixels, a transistor using part of the first semiconductor film as a channel in the row direction, and a pixel electrode connected to a drain electrode of the transistor through a contact hole. In a plan view, a distance (dc) in the row direction from a drain electrode-side edge of the channel to a bottom surface of the contact hole is 0.15 or more times a sub-pixel pitch (dp) in the row direction.
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公开(公告)号:US10797082B2
公开(公告)日:2020-10-06
申请号:US16132509
申请日:2018-09-17
Applicant: Sharp Kabushiki Kaisha
Inventor: Tetsuo Kikuchi , Tohru Daitoh , Hajime Imai , Masahiko Suzuki , Setsuji Nishimiya , Teruyuki Ueda , Kengo Hara
IPC: H01L27/12 , G02F1/1345 , G02F1/1343 , G02F1/1333 , G06F3/041 , G02F1/1362 , H01L29/45 , G06F3/044
Abstract: A TFT array substrate includes gate electrodes constructed from a first metal film, a first insulating film on the first metal film, channels constructed from a semiconductor film on the first insulating film, source electrodes constructed from a second metal film on the semiconductor film, drain electrodes constructed from the second metal film, pixel electrodes constructed from portions of the semiconductor film having reduced resistances, a second insulating film on the semiconductor film and the second metal film, and a common electrode constructed from a transparent electrode film on the second insulating film. The channels overlap the gate electrodes. The source electrodes and the drain electrodes are connected to first ends and second ends of the channels, respectively. The pixel electrodes are connected to the drain electrodes. The second insulating film includes sections overlapping the pixel electrodes without openings. The common electrode overlaps at least the pixel electrodes.
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公开(公告)号:US12100711B2
公开(公告)日:2024-09-24
申请号:US17536648
申请日:2021-11-29
Applicant: SHARP KABUSHIKI KAISHA
Inventor: Masahiko Suzuki , Tetsuo Kikuchi , Setsuji Nishimiya , Kengo Hara , Hitoshi Takahata , Tohru Daitoh
IPC: H01L27/12 , H01L29/66 , H01L29/786
CPC classification number: H01L27/124 , H01L27/1225 , H01L27/127 , H01L29/66742 , H01L29/7869 , H01L29/78696
Abstract: An active matrix substrate includes a plurality of oxide semiconductor TFTs, and a plurality of wiring line connection sections, each of the plurality of wiring line connection sections includes a first connection electrode, an interlayer insulating layer extending over the first connection electrode, a wiring line contact hole formed in an insulating layer including the interlayer insulating layer, the wiring line contact hole exposing a part of a metal oxide layer of a first connection electrode, and a second connection electrode, and the second connection electrode is connected to a part of the metal oxide layer of the first connection electrode in the wiring line contact hole.
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